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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
5 Port 10/100 Ethernet Integrated Switch
Features General Description
IP175A PCB compatible (pins compatible) IP175C/IP175CH integrates a 6-port switch Built in 6 MAC and 5 PHY controller, SSRAM, and 5 10/100 Ethernet Each port can be configured to be 10Base-T, transceivers. Each of the transceivers complies with 100Base-TX the IEEE802.3, IEEE802.3u, and IEEE802.3x 2k MAC address specifications. The DSP approach is utilized for 384k bits packet buffer memory designing transceivers with 0.18um technology; they Support auto-polarity for 10Mbps have high noise immunity and robust performance. Filter/ forward reserved address option Broadcast storm protection IP175C/IP175CH operates in store and forward Auto MDI-MDIX mode. It supports flow control, auto MDI/MDI-X, Support three MII/RMII ports CoS, port base VLAN, bandwidth control, DiffServ, Support SMI with MDC up to 12.5 Mhz SMART MAC and LED functions, etc. Each port can Support tagging & un-tagging be configured to auto-negotiation or forced Support Port base VLAN & tag VLAN 10M/100M, full/half duplexmode. Using an Support CoS EEPROM or pull up/down resistors on specified pins Support port security option can configure the desired options. Support SMART MAC function Support spanning tree protocol Besides a 5-port switch application, Max packet length 1552/ 1536 bytes IP175C/IP175CH supports three MII/RMII ports for Support 8-level bandwidth control router application, which supports 4 LAN ports, one Support Link quality LED for 100Mbps WAN port and one HOME/PNA or Access point. The Support direct, serial and dual color mode LED external MAC can monitor or configure Support one fiber port with far end fault function IP175C/IP175CH by accessing MII registers through for IP175CH only SMI0. Built in linear regulator control circuit Low power consumption MII/RMII port also can be configured to be MAC 0.18um, 128-pin PQFP mode. It is used to interface an external PHY to Support Lead Free package (Please refer to the work as a 5+1 switch. Through SMI1 Order Information) IP175C/IP175CH can monitor and configure external PHY. Note - some features need CPU support, please refer to the detail description inside this data sheet IP175CH supports one fiber port with far end fault function
1/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Table Of Contents
Features................................................................................................................................................... 1 General Description................................................................................................................................. 1 Table Of Contents.................................................................................................................................... 2 Revision History....................................................................................................................................... 4 Comparison Table of IP175A & IP175C/IP175CH................................................................................... 6 Pin diagram (IP175C) .............................................................................................................................. 7 Pin diagram (IP175CH) ........................................................................................................................... 8 1 Pin description................................................................................................................................ 12 2 Functional Description.................................................................................................................... 34 Flow control........................................................................................................................ 34 2.1 Broadcast storm protection ................................................................................................ 34 2.2 Port locking (Port security)................................................................................................. 34 2.3 Port base VLAN ................................................................................................................. 34 2.4 Tag VLAN / Tag and un-tag function .................................................................................. 35 2.5 Tag and un-tag function ........................................................................................ 35 2.5.1 Tag VLAN .............................................................................................................. 35 2.5.2 Tag/ un-tag function and Tag VLAN function in a router application..................... 35 2.5.3 MII/RMII.............................................................................................................................. 36 2.6 SMART MAC...................................................................................................................... 42 2.7 System configuration ............................................................................................ 42 2.7.1 Packet from LAN to WAN ..................................................................................... 44 2.7.2 Packet from WAN to LAN ..................................................................................... 44 2.7.3 Built in regulator ................................................................................................................. 45 2.8 CoS .................................................................................................................................... 46 2.9 Port base priority................................................................................................... 46 2.9.1 Frame base priority ............................................................................................... 46 2.9.2 2.10 Spanning tree ..................................................................................................................... 48 Port states ............................................................................................................. 48 2.10.1 Special tag.......................................................................................................................... 49 2.11 From CPU to switch .............................................................................................. 49 2.11.1 From switch to CPU .............................................................................................. 49 2.11.2 2.12 Static MAC address table................................................................................................... 50 2.13 Serial mode LED................................................................................................................ 51 2.14 LED Blink Timing................................................................................................................ 53 2.15 Serial management interface ............................................................................................. 54 2.16 Force mode of PHY ........................................................................................................... 56 2.17 Reset.................................................................................................................................. 56 2.18 Bandwidth control............................................................................................................... 56 2.19 Fiber mode of port 4 (for IP175CH only)............................................................................ 56 2.20 MII registers of PHY........................................................................................................... 58 2.21 MII registers of Switch controller........................................................................................ 66 3 Electrical Characteristics .............................................................................................................. 101 Absolute Maximum Rating ............................................................................................... 101 3.1 DC Characteristic............................................................................................................. 101 3.2 AC Timing......................................................................................................................... 102 3.3 Reset Timing ....................................................................................................... 102 3.3.1 PHY Mode MII Timing ......................................................................................... 102 3.3.2 MAC Mode MII Timing ........................................................................................ 104 3.3.3 RMII Timing......................................................................................................... 105 3.3.4 SNI Timing .......................................................................................................... 106 3.3.5 SMI Timing .......................................................................................................... 107 3.3.6
U
2/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.7 EEPROM Timing................................................................................................. 109 Thermal Data ................................................................................................................... 109 3.4 Order Information ..........................................................................................................................110 Package Detail .............................................................................................................................. 111
4 5
3/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Revision History
Revision # IP175C-API-R01 IP175C-DS-R01 Change Description Advanced Product Information. 1. Initial release. 2. The difference between IP175C-API-R01 & IP175C-DS-R01 2-1. Remove SCA. 2-2. RMII clock output pin changed. 2-3. Pin 116: CLK_SEL REG_HIGH 1. Modify RMII1 Pin description. 2. MII Register not compatible to IP175A. 3. Add comparison table of IP175A & IP175C. 1. Update page 28 Pin description of X1 2. Add page 99~105 3. Remove POA 4. Remove MII registers PHY 5 and PHY 6 1. Change MDC1 from Pin 53 to Pin 113 2. Add the description of MII0_RXCLK and MII0_TXCLK are in phase. 3. Modify the description of bandwidth control Register. 4. REG_HIGH is internally bounded to GND for the linear regulator to generate a 1.8v voltage source. 1. Modify the value of bit [9:4] of register 4 of PHY 0 ~ PHY 4 from 6'h05 to 6'h18. 2. Add REGOUT to DC charasteritic table. 1. Add Bandwidth control description. 2. Update REGOUT voltage from 1.8v (5%) to 1.82v (6%) 1. Add port security in page 31 2. Add notice for different configuration in router application in page 7 3. Add notice for different configuration in Smart Mac application in page 39 4. Change register setting for 30.1[5:0] from 6'h3f to 6'h30 in page 40 5. Change REGOUT voltage from 1.82v (6%) to 1.70v ~ 1.93v in page 42 6. Modify VIH, VIL in page 97 7. Add reset timing in page 98 8. Change REGOUT voltage from 1.82v (6%) to 1.70v ~ 1.93v in page 9 9. Change band gap resister from 6.2K to 6.19K in page 27 10. Change led_sel [1:0] from {1,0} to {0,1} in page 30 11. Add AVCC & VCC pin list in page 30 1. Remove speed up column in page 49 2. Add in Thermal Data in page 105 3. PHY 30 MII register 12 bit [1] change from * to 1'b1 in page 84 1. Add phy_30_reg_12[8] (bw_en_qm) in page 84 2. Add Note on page 1 for CPU 1. Add the order information for lead free package 1. Change REGOUT voltage upper limit from 1.93v to 2.00v on page 10, 43, 98 2. Change VCC upper limit to 2.00 on page 98 3. Add "All ports link at 10Mbps mode" to REG_OUT Conditions on page 98
IP175C-DS-R02
IP175C-DS-R03
IP175C-DS-R04
IP175C-DS-R05 IP175C-DS-R06 IP175C-DS-R07
IP175C-DS-R08
IP175C-DS-R09 IP175C-DS-R10 IP175C-DS-R11
4/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Revision History
Revision # IP175C-DS-R12 1. 2. 3. 4. 5. 6. 7. 8. Change Description Change to EEPROM register 14~18 or MII register 19~21 on page 32 Add SERIAL_LED_MODE to Pin diagram on page 6 Add pin 112 description for SERIAL_LED_MODE on page 27 Add PHY_31_REG_5[1] SERIAL_LED_MODE on page 97 Add SERIAL_LED_MODE = 0 on page 50 Add description for SERIAL_LED_MODE selection on page 50 Change MII0 MAC mode PHY address to 00000 on page 36 Change P4_FORCE_100 from 22.4 to 20.4 on page 36
IP175Cx-DS-R13
IP175Cx-DS-R14
1. Replace IP175C with IP175C/IP175CH 2. Add "IP175CH support one fiber " to feature list and general description on page 1 3. Modify Comparison Table on page 6 for IP175CH only 4. Add IP175CH Pin diagram on page 8 5. Add FXSD4 Pin description on page 30 6. Add "Fiber mode of port 4 (for IP175CH only)" function description on page 56 7. Modify Order Information on page 111 8. Add Fiber I/O Electrical Characteristics on page 102 1. Modify flow control description on page 34 2. Modify IPL/IPH description on page 12 3. Modify Dual color mode LED Link off status value on page 33 4. Add X1 VIL & X1 VIH on page 102 5. Add 384k bits packet buffer memory on page 1
5/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Comparison Table of IP175A & IP175C/IP175CH
Item/Part Number Pin Assignment Process Package Type Major Block MAC Address AUTO-MDI-MDIX 10M/100M Copper (10BT, 100BaseTx) 100M Fiber (100BaseFX) Max Frame Size 4+1+1: 4Tx+Two MII I/F (RMII I/F) 4+ 3MII 5+1: 5Tx+1 MII I/F SMI I/F(MDC/MDIO) CTRL PHY reg. SNI I/F EEPROM I/F (24C01A) Flow Control-802.3x Flow Control-Backpressure Port Base COS Port Base VLAN QOS- VLAN tag Tag VLAN QOS IPV4 TCP/IP Cos QOS IPV6 TCP/IP Cos Broadcast Storm Protection Power Saving Loop Back Test Port Security Option 8-level Bandwidth Control Link Quantity LED Power down Dual color mode LED Spanning Tree protocol Smart MAC Special address handling Diff serve Direct forwarding IP175C/IP175CH Compatible 0.25um 0.18um 128pin PQFP 128pin PQFP MAC/5ports+PHY/5ports MAC/6ports+PHY/5ports 1K 2K Yes Yes Yes Yes Yes No (Yes for IP175CH only) 1536 1536/1552 (Pin Option) Yes (No) Yes (Yes, MII0, 1 & 2) No Yes No Yes Yes (As data Sheet) Yes (MDC/MDIO*2) Yes Yes (MII0/SNI Option) Yes Yes Yes Yes Yes Yes Yes Yes (Through SMI0) Yes Yes (Through SMI0) Yes Yes (Through SMI0) No Yes Yes Yes No Yes Yes Yes Yes Yes PHY of port 5 Each port No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes IP175A
6/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin diagram (IP175C)
LED_FULL[4] SDATA P0_FORCE_FULL SERIAL_LED_MODE LED_SPEED[4] SCLK P1_FORCE_FULL MII2_MAC_MOD LED_FULL[3] MII2_RXCLK P3_FORCE_FULL RMII2_CLK_IN
LED_SPEED[3] RXD2_0 P4_FORCE_FULL
LED_LINK[3] RXD2_1 P0_FORCE100
LED_LINK[4] COL2 P2_FORCE_FULL
115
128
127
126
114
112
111
110
105
104
124
123
122
121
119
118
117
116
109
108
107
125
120
113
106
103
LED_FULL[1] MII2_TXCLK P4_FORCE_100
LED_FULL[2] RXD2_2 P1_FORCE100
LED_SPEED[2] RXD2_3 P2_FORCE100
LED_LINK[2] RXDV2 P3_FORCE100
RXIM0
X2
MII2_EN MDC1
OSCI (X1)
AGND
RXIP0
GND
REG_OUT
GND
GND
GND
REG_HIGH
VCC
VCC
VCC
NC
AVCC NC TXOP0 TXO M 0 AGND AVCC AGND TXOP1 TXO M 1 AVCC R X IP 1 R X IM 1 AGND AVCC BGRES AGND AGND R X IP 2 R X IM 2 AVCC TXOP2 TXO M 2 AGND AVCC AGND TXOP3 TXO M 3 AVCC R X IP 3 R X IM 3 AGND AGND R X IP 4 R X IM 4 AVCC L O W _ 1 0 M _E N TXOP4 TXOM 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
L E D _ S P E E D [1 ] T X D 2 _ 0 B F _ S T M _E N L E D _ L IN K [1 ] T X D 2 _1 L IN K _ Q L E D _ F U L L [0 ] T X D 2_ 2 X _ E N G ND_O _1 VCC_O _1 L E D _S P E E D [0 ] T X D 2 _ 3 R M II2_ C L K _ O U T
L E D _ L IN K [0 ] T X E N 2 M II0 _ M A C _ M O D E G N D _S R A M VCC_SRAM RESETB L E D _ S E L[1 ] L E D _ S E L[0 ] COL0 P 0 _F O R C E
M II0 _ R X C L K R M II0 _ C L K _ IN RXD0_0 P1_FO RCE RXD0_1 P2_FO RCE RXD0_2 P3_FO RCE RXD0_3 P4_FO RCE RXDV0 GND VCC M II0 _ T X C L K T X D 0 _ 0 P 0 _F O R C E T X D 0 _ 1 P 1 _F O R C E T X D 0 _ 2 P 2 _F O R C E T X D 0 _ 3 P 3 _F O R C E TXEN0 P4_FO RCE P 4 M II_ S N I P 4 E X T M D IO 1 G ND _O_2 VCC_O _2 MDC0 M D IO 0 C O L 1 F IL T E R _ R S V _ D A M II1 _ R X C L K R M II1 _ M A C _ C L K _ IN R M II0 _ C L K _ O U T
IP 1 7 5 C
83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 55 56 57 58 59 60 61 62 63 64
RXD1_0 M AC_X_EN RXD1_1 LO NG _PKT R X D 1 _ 2 A G IN G R M II1 _ P H Y _ C L K _ O U T
AVCC
NC
TXD1_3 RMII1_MAC_CLK_OUT
TXD1_2 RMII1_PHY_CLK_IN
SDA
7/111 Copyright (c) 2004, IC Plus Corp.
RXD1_3 P4_HIGH
MII1_PHY_MOD
RXDV1 COS_EN
MII1_DIS
TXD1_1
GND
VCC
GND
NC
NC
VCC
TXEN1
SCL RMII_EN
MII1_TXCLK
GND
TEST2
TXD1_0
VCC
AGND
GND
NC
VCC
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin diagram (IP175CH)
LED_FULL[4] SDATA P0_FORCE_FULL SERIAL_LED_MODE LED_SPEED[4] SCLK P1_FORCE_FULL MII2_MAC_MOD LED_FULL[3] MII2_RXCLK P3_FORCE_FULL RMII2_CLK_IN
LED_SPEED[3] RXD2_0 P4_FORCE_FULL
LED_LINK[3] RXD2_1 P0_FORCE100
LED_LINK[4] COL2 P2_FORCE_FULL
115
128
127
126
114
112
111
110
105
104
124
123
122
121
119
118
117
116
109
108
107
125
120
113
106
103
LED_FULL[1] MII2_TXCLK P4_FORCE_100
LED_FULL[2] RXD2_2 P1_FORCE100
LED_SPEED[2] RXD2_3 P2_FORCE100
LED_LINK[2] RXDV2 P3_FORCE100
RXIM0
X2
MII2_EN MDC1
OSCI (X1)
AGND
RXIP0
GND
REG_OUT
GND
GND
GND
REG_HIGH
VCC
VCC
VCC
NC
AVCC NC TXOP0 TXO M 0 AGND AVCC AGND TXOP1 TXO M 1 AVCC R X IP 1 R X IM 1 AGND AVCC BGRES AGND AGND R X IP 2 R X IM 2 AVCC TXOP2 TXO M 2 AGND AVCC AGND TXOP3 TXO M 3 AVCC R X IP 3 R X IM 3 AGND AGND R X IP 4 R X IM 4 AVCC L O W _ 1 0 M _E N TXOP4 TXOM 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
L E D _ S P E E D [1 ] T X D 2 _ 0 B F _ S T M _E N L E D _ L IN K [1 ] T X D 2 _1 L IN K _ Q L E D _ F U L L [0 ] T X D 2_ 2 X _ E N G ND_O _1 VCC_O _1 L E D _S P E E D [0 ] T X D 2 _ 3 R M II2_ C L K _ O U T
L E D _ L IN K [0 ] T X E N 2 M II0 _ M A C _ M O D E G N D _S R A M VCC_SRAM RESETB L E D _ S E L[1 ] L E D _ S E L[0 ] COL0 P 0 _F O R C E
M II0 _ R X C L K R M II0 _ C L K _ IN RXD0_0 P1_FO RCE RXD0_1 P2_FO RCE RXD0_2 P3_FO RCE RXD0_3 P4_FO RCE RXDV0 GND VCC M II0 _ T X C L K T X D 0 _ 0 P 0 _F O R C E T X D 0 _ 1 P 1 _F O R C E T X D 0 _ 2 P 2 _F O R C E T X D 0 _ 3 P 3 _F O R C E TXEN0 P4_FO RCE P 4 M II_ S N I P 4 E X T M D IO 1 G ND _O_2 VCC_O _2 MDC0 M D IO 0 C O L 1 F IL T E R _ R S V _ D A M II1 _ R X C L K R M II1 _ M A C _ C L K _ IN R M II0 _ C L K _ O U T
IP 1 7 5 C H
83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 55 56 57 58 59 60 61 62 63 64
RXD1_0 M AC_X_EN RXD1_1 LO NG _PKT R X D 1 _ 2 A G IN G R M II1 _ P H Y _ C L K _ O U T
AVCC
NC
TXD1_3 RMII1_MAC_CLK_OUT
TXD1_2 RMII1_PHY_CLK_IN
SDA
8/111 Copyright (c) 2004, IC Plus Corp.
RXD1_3 P4_HIGH
MII1_PHY_MOD
RXDV1 COS_EN
MII1_DIS
TXD1_1
GND
VCC
GND
NC
NC
VCC
TXEN1
SCL RMII_EN
MII1_TXCLK
GND
FXSD4
TEST2
TXD1_0
VCC
AGND
GND
VCC
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
5-port switch application When pin 74 P4EXT is pulled low, all MII/RMII ports are disabled, and IP175C/IP175CH works as a 5-port switch. MAC5 is not used in this application.
IP175C
switch engine MAC5 MAC0 ..... MAC4
(MAC5 is unused)
PHY 0
PHY 1
PHY 2
PHY 3
PHY 4
TP
9/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Router application using one MII/RMII port (can be configured to 4LAN+1WAN, 3LAN+2WAN, 2LAN+3WAN or 1LAN+4WAN) p4ext 1 mii1_dis 1 mii2_en 0 p4mii_sni 0 rmii_en x mii0_mac_mod 0 mii2_mac_mod x
Switch Engine
MAC 0 PHY 0 MAC 1 PHY 1 MAC 2 PHY 2 MAC 3 PHY 3
MII0 / RMII0 MAC 5 MAC 4 PHY 4 CPU CPU
TP TP
Router application using two-MII/RMII ports p4ext 1 mii1_dis 0 mii2_en 0 p4mii_sni 0 rmii_en x mii0_mac_mod 0 mii2_mac_mod x
Switch Engine
MAC 0 PHY 0 MAC 1 PHY 1 MAC 2 PHY 2 MAC 3 PHY 3
MII0 / RMII0 MAC 5 MAC 4 CPU MII1 / RMII1
X
PHY 4
TP
Note: PHY4 is an independent PHY in this application
10/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Router application using two-MII/RMII ports (another option)
p4ext 1
mii1_dis 0
mii2_en 0
p4mii_sni 0
rmii_en x
mii0_mac_mod 0
mii1_phy_mod 0
Switch Engine
MAC 0 PHY 0 MAC 1 PHY 1 MAC 2 PHY 2 MAC 3 PHY 3
MII0 / RMII0 MAC 5 MII1 / RMII1 MAC 4 Access Point / HomePNA/ VOIP CPU
X
PHY 4
TP
Note: PHY4 is disable and MII1/RMII1 is mac mode in this application.
Router application using three-MII/RMII ports
p4ext 1
mii1_dis 0
mii2_en 1
p4mii_sni 0
rmii_en x
mii0_mac_mod 0
mii2_mac_mod 0
Switch Engine
MAC 0 PHY 0 MAC 1 PHY 1 MAC 2 PHY 2 MAC 3 PHY 3
MII0 / RMII0 MAC 5 MII2 / RMII2 MAC 4 Access Point / HomePNA/ VOIP CPU
X
PHY 4
MII1 / RMII1
TP
Note: PHY4 is an independent PHY in this application
11/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
1
I O IPL IPH
Pin description
Description
Input pin Output pin Input pin with internal pull low 50M ohm Input pin with internal pull high 50M ohm
Type
Type IPL1 IPH1 IPL2 IPH2
Description Input pin with internal pull low 22.8k ohm
Input pin with internal pull high 22.8k ohm Input pin with internal pull low 92.6k ohm Input pin with internal pull high 113.8k ohm
Pin No. Analog 120
Label
REG_OUT
Type
O Regulator output.
Description
The internal linear regulator uses this pin to control external transistor to generates a voltage source between 1.70v ~ 2.00v. IP175C/IP175CH uses the DVCC/AVCC as feedback voltage. 116 REG_HIGH I Regulator output selection is internally bounded to GND.
12/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin description (continued) Pin No. Label Type Description
LED pins used as initial setting (the setting is latched at the end of reset) 102 BF_STM_EN IPL1 Broadcast storm protection enable 1: enable 0: disable (default)
A port begins to drop packets if it receives broadcast packets more than the threshold defined in MII register 30.11[15:14] bq_stm_thr_sel [1:0] or EEPROM register 59[7:6] 101 LINK_Q IPH1 Link quality 1: enable (default) 0: disable When the function is enabled, besides link on/off status, activity status, link LED shows link quality. The link LED will be flash (on: 2sec / off: 2sec) when the SNR of received signal is lower than the desired value for normal operation. 100 X_EN IPH1 IEEE802.3X/ back pressure enable 1: enable (default) 0: disable This pin doesn't set the flow control of MII0 port. Pin 67 MAC_X_EN sets the flow control of MII0 port.
13/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin description (continued) Pin No. Label Type Description
MII pins used as initial setting (the setting is latched at the end of reset) 69 FILTER_RSV _DA IPL Filter packets with reserved DA (0180c20002~f) 1: Filter the packets 0: Forward the packets (default)
It is valid only if p4ext is pulled LOW. 66 LONG_PKT IPL Max forwarded packet length 1: 1552 bytes 0: 1536 bytes (default) It is valid only if p4ext is pulled low. Address aging enable 1: enable, aging time is around 280s (default), 0: disable It is recommended to disable the aging function, if port-locking function is enabled. It is valid only if p4ext is pulled low. 64 P4_HIGH IPL2 Port4 is set to be high priority port 1: enable, 0: disabled (default) Packets received from port4 are handled as high priority packets if the feature is enabled. It is valid only if p4ext is pulled low. 63 COS_EN IPL2 Class of service enable 1: enable 0: disabled (default) Packets with high priority tag are handled as high priority packets for all ports if the feature is enabled. It is valid only if p4ext is pulled low.
65
AGING
IPH2
14/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin description (continued) Pin No. Label Type
IPL
Description
10M low power mode enable 1: 10M low power mode, the trasmit amplitude is depressed in 10M mode for power saving. 0: 10M normal mode (default)
Initial setting 36 LOW_10M_EN
15/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin description (continued) Pin No. Label Type Description External MII port setting (the setting is latched at the end of reset) 74 P4EXT IPL External MII port enable 1: MII interface configuration is enabled. 0: External MII interface is disabled and IP175C/IP175CH works as a 5-port switch (default).
The configuration function of pin Px_FORCE, FILTER_RSV_DA, MAC_X_EN, LONG_PKT, AGING, P4_HIGH and COS_EN are disabled when this pin is pulled high. RMII enable for all MII ports. 1: All MII/RMII interfaces work in RMII mode 0: All MII/RMII interfaces work in MII mode (default). It is valid only if P4EXT is pulled high. This pin defines the initial setting of all MII ports. Each port can be configured as MII or RMII by programming MII register 31.5[10:8]. Flow control enable for external MII ports 1: enable (default), 0: disable It is valid only if P4EXT is pulled low. External MII0 port MAC mode MII0 is connected to MAC5 of IP175C/IP175CH. 1: MII0 works as a MAC and should be connected to an external PHY. 0: MII0 works as a PHY and should be connected to an external MAC device (default).
53
RMII_EN
IPL
67
MAC_X_EN
IPH2
96
MII0_MAC_MOD
IPL1
54
MII1_PHY_MOD (SDA)
It is valid only if P4EXT is pulled high. IPH/O External MII1 source port selection 1: MII1 is connected to PHY4 of IP175C/IP175CH. It should be connected to an external MAC device. 0: MII1 is connected to MAC4 of IP175C/IP175CH. It should be connected to an external PHY. IPL It is valid only if P4EXT is pulled high and MII1_DIS is pulled low. External MII2 port MAC mode MII2 is connected to MAC4 of IP175C/IP175CH. 1: MII2 works as a MAC and should be connected to an external PHY. 0: MII2 works as a PHY and should be connected to an external MAC device (default).
111
MII2_MAC_MOD
113
MII2_EN
It is valid only if P4EXT is pulled high and MII2_EN is pulled high. IPL/O MII2 enable 1: MII2 is enabled. It is note that LED is changed to serial mode automatically. User should not enable MII2 if pin 54 MII1_PHY_MOD is pulled low. 0: MII2 is disabled (default). It is valid only if P4EXT is pulled high. The configuration function of pin Px_FORCE_FULL, Px_FORCE_100, BF_STM_EN, LINK_Q, X_EN, and MII0_MAC_MODE are disabled when this pin is pulled high. It becomes an output pin MDC1 after reset.
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Pin description (continued) Pin No. Label Type
IPL SNI enable for MII0 1: SNI interface 0: MII interface (default). It is valid only is P4EXT is pulled high and RMII_EN is pulled low. It is valid for MII0 only. 51 MII1_DIS IPL Disable MII1 1: MII1 is disabled. It is for router application with one-MAC CPU. 0:.MII1 is enabled. PHY4 is an independent PHY and can be access through MII1. It is for router application with two-MAC CPU (default). It is valid only if P4EXT is pulled high.
Description
External MII port setting 75 P4MII_SNI
Configuration summary mode p4ext mii1_dis MII/RMII0 MII/ PHY mode 1 X MII/ MAC mode 1 X RMII 1 X SNI/ PHY mode 1 X SNI/ MAC mode 1 X MII/RMII1 MII/ PHY mode RMII MII/RMII2 MII/ PHY mode MII/ MAC mode RMII
1 1 1 1 1 0 0 X X X
mii2_en p4mii_sni rmii_en mii0_mac_mod mii2_mac_mod
X X X X X X X 1 1 1 0 0 0 1 1 X X X X X 0 0 1 0 0 0 1 0 0 1 0 1 X 0 1 X X X X X X X X X X X X 0 1 X
Note: RMII_EN takes precedence of P4MII_SNI.
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0) 89 MII0_RXCLK O MII receive clock
MII0_RXCLK and MII0_TXCLK are the same clock source and in phase. 81 80, 79, 78, 77 76 MII0_TXCLK TXD0_0, TXD0_1, TXD0_2, TXD0_3 TXEN0 O IPL2 MII transmit clock MII transmit data It is sampled at the rising edge of MII0_TXCLK. IPL2 MII transmit enable It is used to frame TXD0[3:0]. It is sampled at the rising edge of MII0_TXCLK. 90 COL0 O MII collision It is active when MII0 is half duplex and a collision event happens. 84 RXDV0 O MII receive data valid It is used to frame RXD0[3:0]. It is sent out at the falling edge of MII0_RXCLK. 88, 87, 86, 85 RXD0_0, RXD0_1, RXD0_2, RXD0_3 O MII receive data It is sent out at the falling edge of MII0_RXCLK.
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0) 81 MII0_TXCLK I MII transmit clock
It is an input clock and it is connected to MII_TXCLK of external PHY. 80, 79, 78, 77 TXD0_0, TXD0_1, TXD0_2, TXD0_3 O MII transmit data It is connected to MII_TXD of external PHY. It is sent out at the rising edge of MII0_TXCLK. MII transmit enable It is an output signal and is connected to MII_TXEN of external PHY. It is sent out at the rising edge of MII0_TXCLK. 90 COL0 IPL2 MII collision It is an input signal and is connected to the MII_COL of external PHY. 84 RXDV0 I MII receive data valid It is an input signal and is connected to the MII_RXDV of external PHY. RXDV0 is used to frame RXD0[3:0]. 88, 87, 86, 85 RXD0_0, RXD0_1, RXD0_2, RXD0_3 I Receive data It is NRZ data and is connected MII_RXD[3:0] of external PHY. It is received at the rising edge of MII0_RXCLK. 89 MII0_RXCLK I MII receive clock
76
TXEN0
O
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External MII1 interface (PHY mode, MII1_PHY_MOD=1, P4EXT=1) 62 MII1_TXCLK O MII Transmit clock 61, 60, TXD1_0, TXD1_1, IPL2 MII transmit data 59, 58 TXD1_2, TXD1_3 It is sampled at the rising edge of MII1_TXCLK. 57 TXEN1 IPL2 MII transmit enable
It is used to frame TXD1[3:0]. It is sampled at the rising edge of MII1_TXCLK. 69 COL1 O MII collision It is active when MII1 is half duplex and a collision event happens. MII receive data valid It is used to frame RXD1[3:0]. It is sent out at the falling edge of MII1_RXCLK. 67, 66, 65, 64 68 RXD1_0, RXD1_1, RXD1_2, RXD1_3 MII1_RXCLK O MII receive data It is sent out at the falling edge of MII1_RXCLK. O MII receive clock
63
RXDV1
O
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External MII2 interface (PHY mode, MII2_MAC_MOD=0, MII2_EN=1) 109 MII2_RXCLK O MII receive clock 103 MII2_TXCLK O MII transmit clock 102, 101, TXD2_0, TXD2_1, IPL2 MII transmit data 100, 97 TXD2_2, TXD2_3 IPH1 IPH1 It is sampled at the rising edge of MII2_TXCLK. IPL2 96 TXEN2 IPL2 MII transmit enable
It is used to frame TXD0[3:0]. It is sampled at the rising edge of MII2_TXCLK. 110 COL2 O MII collision It is active when MII2 is half duplex and a collision event happens. 104 RXDV2 O MII receive data valid It is used to frame RXD0[3:0]. It is sent out at the falling edge of MII2_RXCLK. 108, 107, 106, 105 RXD2_0, RXD2_1, RXD2_2, RXD2_3 O MII receive data It is sent out at the falling edge of MII2_RXCLK.
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External MII2 interface (MAC mode, MII2_MAC_MOD=1, MII2_EN=1) 103 MII2_TXCLK I MII transmit clock
It is an input clock and it is connected to MII_TXCLK of external PHY. 102, 101, 100, 97 TXD2_0, TXD2_1, TXD2_2, TXD2_3 O MII transmit data It is connected to MII_TXD of external PHY. It is sent out at the rising edge of MII2_TXCLK. MII transmit enable It is an output signal and is connected to MII_TXEN of external PHY. It is sent out at the rising edge of MII2_TXCLK. 110 COL2 IPL2 MII collision It is an input signal and is connected to the MII_COL of external PHY. 104 RXDV2 I MII receive data valid It is an input signal and is connected to the MII_RXDV of external PHY. RXDV2 is used to frame RXD2[3:0]. 108, 107, 106, 105 RXD2_0, RXD2_1, RXD2_2, RXD2_3 I Receive data It is NRZ data and is connected MII_RXD[3:0] of external PHY. It is received at the rising edge of MII2_RXCLK. 109 MII2_RXCLK I MII receive clock
96
TXEN2
O
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External RMII0 interface (RMII_EN=1, P4EXT=1) 88, 87 RXD0_0, RXD0_1 I RMII receive data
It is connected RMII_RXD[1:0] of external PHY or RMII_TXD[1:0] of external MAC. 84 RXDV0 I RMII receive data valid It is connected RMII_RXDV of external PHY or RMII_TXEN of external MAC. 80, 79 TXD0_0, TXD0_1 O RMII transmit data It is connected RMII_RXD[1:0] of external MAC or RMII_TXD[1:0] of external PHY. 76 TXEN0 O RMII transmit enable It is connected RMII_RXDV of external MAC or RMII_TXEN of external PHY. 77 89 RMII0_CLK_OUT RMII0_CLK_IN O I A 50Mhz reference clock output for other RMII devices 50Mhz RMII reference clock input
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External RMII1 interface (RMII_EN=1, MII1_DIS=0, MII1_PHY_MOD=1, P4EXT=1) 67, 66 RXD1_0, RXD1_1 O RMII receive data
It is connected to RMII_TXD[1:0] RMII_RXD[1:0] of external MAC. 63 RXDV1 O RMII receive data valid It is connected to RMII_TXEN of external PHY or RMII_RXDV of external MAC. 61, 60 TXD1_0, TXD1_1 I RMII transmit data It is connected to RMII_RXD[1:0] of external PHY or RMII_TXD[1:0] of external MAC. 57 TXEN1 I RMII transmit enable It is connected to RMII_RXDV of external PHY or RMII_TXEN of external MAC. 65 59 RMII1_PHY_CLK _OUT RMII1_PHY_CLK _IN O I A 50Mhz reference clock output for other RMII devices 50Mhz RMII reference clock input of external PHY or
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External RMII1 interface (RMII_EN=1, MII1_DIS=0, MII1_PHY_MOD=0, P4EXT=1) 67, 66 RXD1_0, RXD1_1 I RMII receive data
It is connected to RMII_RXD[1:0] of external PHY or RMII_TXD[1:0] of external MAC. 63 RXDV1 I RMII receive data valid It is connected to RMII_RXDV of external PHY or RMII_TXEN of external MAC. 61, 60 TXD1_0, TXD1_1 O RMII transmit data It is connected to RMII_RXD[1:0] of external MAC or RMII_TXD[1:0] of external PHY. 57 TXEN1 O RMII transmit enable It is connected to RMII_RXDV of external MAC or RMII_TXEN of external PHY. 58 68 RMII1_MAC_CLK _OUT RMII1_MAC_CLK _IN O I A 50Mhz reference clock output for other RMII devices 50Mhz RMII reference clock input
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Data Sheet
Pin description (continued) Pin No. Label Type Description
External RMII2 interface (RMII_EN=1, MII2_EN=1, P4EXT=1) 108, 107 RXD2_0, RXD2_1 I RMII receive data
It is connected RMII_RXD[1:0] of external PHY or RMII_TXD[1:0] of external MAC. 104 RXDV2 I RMII receive data valid It is connected RMII_RXDV of external PHY or RMII_TXEN of external MAC. 102,101 TXD2_0, TXD2_1 O RMII transmit data It is connected RMII_RXD[1:0] of external MAC or RMII_TXD[1:0] of external PHY. 96 TXEN2 O RMII transmit enable It is connected RMII_RXDV of external MAC or RMII_TXEN of external PHY. 97 109 RMII2_CLK_OUT RMII2_CLK_IN O I A 50Mhz reference clock output for other RMII devices 50Mhz RMII reference clock input
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Data Sheet
Pin description (continued) Pin No. Label Type Description
Force mode (the setting is latched at the end of reset) 85, 76 P4_FORCE IPL2 Port4 works at force mode. 1: force mode, disable port4 NWAY capability 0: auto-negotiation with all capability enabled (default)
It's set by pin 85 if MII0 is in PHY mode and it's set by pin 76 if MII0 is in MAC mode. It is valid only if p4ext is pulled low. 86, 77 P3_FORCE IPL2 Port3 works at force mode. 1: force mode, disable port3 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 86 if MII0 is in PHY mode and it's set by pin 77 if MII0 is in MAC mode. It is valid only if p4ext is pulled low. 87, 78 P2_FORCE IPL2 Port2 works at force mode. 1: force mode, disable port2 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 87 if MII0 is in PHY mode and it's set by pin 78 if MII0 is in MAC mode. It is valid only if p4ext is pulled low. 88, 79 P1_FORCE IPL2 Port1 works at force mode. 1: force mode, disable port1 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 88 if MII0 is in PHY mode and it's set by pin 79 if MII0 is in MAC mode. It is valid only if p4ext is pulled low. 90, 80 P0_FORCE IPL2 Port0 works at force mode. 1: force mode, disable port0 NWAY capability 0: auto-negotiation with all capability enabled (default) It's set by pin 90 if MII0 is in PHY mode and it's set by pin 80 if MII0 is in MAC mode. It is valid only if p4ext is pulled low.
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Data Sheet
Pin description (continued) Pin No. Label Type Description
Force mode (the setting is latched at the end of reset) 103 P4_FORCE100 IPL1 Force port4 work at 100M or 10M. 1: force 100M 0: force 10M (default)
It is used to force speed of the sixth switch port (MAC5) if P4EXT is pulled high. The configuration function is disabled when MII2_EN is pulled high. 104 P3_FORCE100 IPL1 Force port3 work at 100M or 10M. 1: force 100M 0: force 10M (default) It is used to force speed of the fifth switch port (MAC4) if P4EXT is pulled high. The configuration function is disabled when MII2_EN is pulled high. 105 P2_FORCE100 IPL1 Force port2 work at 100M or 10M. 1: force 100M 0: force 10M (default) The configuration function is disabled when MII2_EN is pulled high. Force port1 work at 100M or 10M. 1: force 100M 0: force 10M (default) The configuration function is disabled when MII2_EN is pulled high. Force port0 work at 100M or 10M. 1: force 100M 0: force 10M (default) The configuration function is disabled when MII2_EN is pulled high.
106
P1_FORCE100
IPL1
107
P0_FORCE100
IPL1
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Data Sheet
Pin description (continued) Pin No. Label Type Description
Force mode (the setting is latched at the end of reset) 108 P4_FORCE_FULL IPL1 Force port4 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default)
It is used to force duplex of the sixth switch port (MAC5) if P4EXT is pulled high. The configuration function is disabled when MII2_EN is pulled high. 109 P3_FORCE_FULL IPL1 Force port3 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) It is used to force duplex of the fifth switch port (MAC4) if P4EXT is pulled high. The configuration function is disabled when MII2_EN is pulled high. 110 P2_FORCE_FULL IPL1 Force port2 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) The configuration function is disabled when MII2_EN is pulled high. Force port1 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) The configuration function is disabled when MII2_EN is pulled high. 112 P0_FORCE_FULL IPL1 Force port0 work at full duplex or half duplex 1: force full duplex 0: force half duplex (default) The configuration function is disabled when MII2_EN is pulled high. When MII2_EN, this pin is for SERIAL_LED_MODE setting
111
P1_FORCE_FULL IPL1
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Data Sheet
Pin description (continued) Pin No. Label Type
I TP receive
Description
Transceiver 127, 128, RXIP0, RXIM0, 11, 12, RXIP1, RXIM1, 18, 19, RXIP2, RXIM2, 29, 30, RXIP3, RXIM3, 33, 34 RXIP4, RXIM4 3, 4, TXOP0, TXOM0, 8, 9, TXOP1, TXOM1, 21, 22, TXOP2, TXOM2, 26, 27, TXOP3, TXOM3, 37, 38 TXOP4, TXOM4 15 BGRES
O
TP transmit
O
Band gap resister. It is connected to GND through a 6.19 k ohm resistor. Please refer to application circuit for more information.
125, 41, NC 42, 43, 44 44 FXSD4 (IP175CH only)
I I 100Base-FX Signal detect Port 4 of IP175C can be configured to TP or FX. If FXSD4 is connected to SD of a fiber MAU, port 4 is a fiber port. If FXSD4 is tied to GND, the port 4 is a TP port. If port 4 is defined to be a fiber port, its speed is forced to be 100M and its duplex is defined in its MII register 4.0.8. Please refer section 2.19 on page 56 for more detail description.
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Data Sheet
Pin description (continued) Pin No. Misc. 123
X1
Label
Type
I
Description
System clock input or crystal input It is recommended to connect X1 and X2 to a crystal. If the clock source is from another chip, the clock should be active at least for 1ms before pin 93 RESETB de-asserted.
122 93 52
X2 RESETB TEST2
O I IPL
Crystal output Reset, low active Test mode enable It should be connected to GND for normal operation.
EEPROM 53 SCL
IPL/O After reset, it is used as clock pin SCL of EEPROM. Its period is longer than 10us. IP175C/IP175CH stops reading EEPROM if it finds there is no 55AA pattern in address 0. After reading EEPROM, this pin becomes an input pin. IPH/O After reset, it is used as data pin SDA of EEPROM. After reading EEPROM, this pin becomes an input pin. It is pulled up in 24C01A application circuit. IPL SMI0 The external MAC device uses the interface to access IP175C/IP175CH's MII registers.
54
SDA
SMI 71, 70
MDC0, MDIO0
113, 74
MDC1, MDIO1
IPL/O SMI1 IP175C/IP175CH uses the interface to polling the MII registers of external PHY to get its status. It is active only if p4ext is pulled high. If the external PHY doesn't support SMI, the polling result will be 16'hFFFF, and IP175C/IP175CH suppose the link status is good.
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Data Sheet
Pin description (continued) Pin No. LED 92, 91 Label
LED_SEL[1:0]
Type
IPH
Description
LED output mode selection. LED_SEL[1:0]=00: LED mode 0, LED_SEL[1:0]=01: LED mode 1, dual color mode LED_SEL[1:0]=10: LED mode 2, LED_SEL[1:0]=11: LED mode 3 (default)
110, 107, LED_LINK[4:0] 104, 101, 96
O
Link, Activity (output after reset) LED mode0: 100M Link + Activity (same as mode 2) LED mode1: LED mode2, 100M Link + Activity (1: 100M Link fail, 0: 100M Link ok and no activity, flash: 100M Link ok and TX/RX activity) LED mode3: Link + Activity (1: link fail, 0: link ok, flash: Link ok and TX/ RX activity)
111, 108, LED_SPEED[4:0] 105, 102, 97
O
Speed (output after reset) LED mode0: (1: no collision, flash: collision) (note*) LED mode1: LED mode2: Full/half: (1: half, 0: full, flash: collision) LED mode3: (1: speed=10M, 0: speed=100M)
112, 109, LED_FULL[4:0] 106, 103, 100
O
Full/half, Link (output after reset) LED mode0, 10M Link + Activity (same as mode 2) LED mode1, same as mode 3 LED mode2, 10M Link + Activity (1: 10M Link fail, 0: 10M Link ok and no activity, flash: 10M Link ok and TX/RX activity) LED mode3: Full/half: (1: half, 0: full, flash: collision)
Note: LED_SPEED[0] shows collision information for all ports. LED_SPEED[4:1] is undefined.
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Data Sheet
Pin description (continued) Pin No. Label Type Description
Dual color mode LED (It is active when LED_SEL[1:0] is {0,1}.) 110, 107, LED_LINK[4:0] Application circuit O 104, 101, L E D _ L IN K 96 111, 108, LED_SPEED[4:0] O 1 0 0 M lin k /a c t 105, 102, 97
LED_SPEED
1 0 M lin k /a c t
Type Link off 100M link 100M link/ Activity 10M link 10M link/ Activity 112, 109, LED_FULL[4:0] 106, 103, 100 O O O O O O 0 1
LED_LINK 0 0 0 1
LED_SPEED
Flash 0 0
Flash
Full/half, Link (output after reset) Full/half: (1: half, 0: full, flash: collision)
Serial LED (MII2_EN=1) 112 SDATA 111 SCLK
O O
LED serial data LED serial clock Normal mode: 312.5KHz, Speed_up mode: 10MHz
Power 72, 98
1, 6, 10, 14, 20, 24, 28, 35, 40 46, 47, 50, 55, 82, 94, 114, 115, 124
VCC_O_1, VCC_O_2 AVCC
3.3V power 1.8v power
VCC
1.8v power
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Data Sheet
2
2.1
Functional Description
Flow control
IP175C/IP175CH supports the standard 802.3X flow control frames on both transmit and receive sides. On the receive side, if IP175C/IP175CH receives a pause control frame, the IP175C/IP175CH will defer transmitting next normal frame; on the transmit side, IP175C/IP175CH issues pause control frame (Pause On, time slot count = 0xffff) to remote station when the output queue of the destination port is higher than high water mark threshold. When the output queue of the destination port is lower than low water mark threshold, IP175C/IP175CH issues pause control frame (Pause Off, time slot count = 0) to restart transmition. Besides, IP175C/IP175CH provides an additional protect function, when it issues continuous 16 times of Pause ON frame (network abnormal), no more Pause ON frame will be send. When CoS is enabled, IP175C/IP175CH may disable the flow control function for a short term to guarantee the bandwidth of high priority packets. A port disables its flow control function for 2 ~ 3 seconds when it receives a high priority packet. It doesn't transmit pause frame or jam pattern during the period but it still responses to pause frame or jam pattern.
2.2
Broadcast storm protection
A port of IP175C/IP175CH begins to drops broadcast packets if the received broadcast packets are more than the threshold defined in MII register 30.11[15:14] or EEPROM register 59[7:6] bq_stm_thr_sel [1:0] in
10ms (100Mbps) or 100ms (10Mbps)
The function can be enabled by pulling high pin 102 BF_STM_EN or programming MII register 29.18.11.
2.3
Port locking (Port security)
IP175C/IP175CH supports port locking. Each port can be configured individually by programming MII register 30.10[5:0] or EEPROM 57[5:0]. User has to reset IP175C/IP175CH to disable the function by writing 16'h175C to MII register 30.0 after enabling this function. IP175C/IP175CH locks first MAC address if the function is enabled. Any packet with MAC address not equal to the locked one will be dropped. The aging function is recommended to be disabled, if port locking is enabled.
2.4
Port base VLAN
IP175C/IP175CH supports port base VLAN functions. It separates IP175C/IP175CH into some groups (VLAN). A port is limited to communicate with other ports within the same group when the function is enabled. Frames will be limited in a VLAN group and will not be forwarded out of this VLAN group. A port can be assigned to one or more VLAN groups. The members (ports) of a VLAN group are assigned by programming EEPROM register 14~18 or MII register 19~21.
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2.5
2.5.1
Tag VLAN / Tag and un-tag function
Tag and un-tag function
IP175C/IP175CH inserts or removes a tag of a frame if tagging/ un-tagging function is enabled. It is enabled by programming MII register 29.23. The operation is illustrated as follows. The tag information is defined in MII register 29.24~29.30 and EEPROM register 24~38.
Frame type of the received packet
Untagged
Priority-tagged (VLAN ID=0)
VLAN-tagged
The operation of a port which forwards the packet Forward to a untagged filed Forward to a tagged field Forward the packet without modification 1. Insert a tag using the default VLAN tag value of the source port 2. Calculate new CRC 3. The default VLAN tag value is defined in the MII register 29.24~29.30. 1. Strip tag 1. Keep priority field. 2. Calculate new CRC 2. Replace the tag with the default VLAN tag value of the source port 3. Calculate new CRC 4. The default VLAN tag value is defined in the MII register 29.24~29.30. 1. Strip tag Forward the packet without modification 2. Calculate new CRC
2.5.2
Tag VLAN
If tag VLAN function is enabled (MII register 30.9.7 TAG_VLAN_EN is logic high), IP175C/IP175CH forwards a packet according to MAC address and VLAN output port masks, defined in MII register 30.1~30.8. A tagged packet is forwarded to the ports belonging to the same VLAN of the packet. One of the sixteen VLAN output port masks is selected by VID index, which is four bits selected from VID field in a tag. VID index is defined in MII register 30.9[6:4] VID_IDX_SEL. For example, VLAN output port mask 1 is selected if VID index selected by VID_IDX_SEL is equal to 1. IP175C/IP175CH handles an un-tagged packet using the default VLAN tag value of its source port. A packet with VID equal to 12'b0 will be handled as un-tag frame.
2.5.3
Tag/ un-tag function and Tag VLAN function in a router application
Tag/ un-tag and Tag VALN are necessary in a router application with one-MAC CPU, MII0 is connected to CPU and MII1 is disabled (DIS_MII1=1). PHY0~4 are connected to switching engine MAC 0~4 and MII0 is connected to switching engine MAC5. In this application, MII0 is defined as a tagged port and the other ports (port 0~4) are defined as un-tagged ports. IP175C/IP175CH inserts VLAN tag into packets withsource port information when it forwards the packets to MII0. The VLAN tags are defined in MII register 29.24~29.30. CPU can identify the source port of a packet by examining the VLAN tag. CPU inserts VLAN tag into packets with destination port information following the content in MII register 29.24~29.30 when it sends packets to MII0. IP175C/IP175CH forwards a packet from MII0 to the appropriate port according to the MAC address and VLAN tag. IP175C/IP175CH removes the VLAN tag when it forwards the packet.
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2.6 MII/RMII
IP175C/IP175CH supports three MII/RMII ports. The block diagram and detail configuration are shown below. It is noted that MII2 and MII1 MAC mode can't be enabled at the same time. That is, user should not use MII2 if pin 54 MII1_PHY_MOD is pulled low.
MII0 / RMII0 MAC 5 MII2 / RMII2 MAC 0 PHY 0 MAC 1 PHY 1 MAC 2 PHY 2 MAC 3 PHY 3 MAC 4 MII1 / RMII1 PHY 4 Access Point / HomePNA/ VOIP CPU
Switch Engine
TP
I/F MII0 MII MII RMII SNI SNI MII1 MII MII RMII RMII
mode
Int
ext
p4ext
mii1 _dis
X X X X X 0 0 0 0 X X X
mii2 _en
X X X X X X 0 X 0 1 1 1
p4mii rmii_ mii0_mac mii1_phy mii2_mac _sni en _mod _mode _mod
0 0 0 1 1 X X X X X X X 0 0 1 0 0 0 0 1 1 0 0 1 0 1 X 0 1 X X X X X X X X X X X X 1 0 1 0 X X X X X X X X X X X X 0 1 X
PHY mode MAC5 MAC MAC mode MAC5 PHY MAC MAC5 Note1 PHY mode MAC5 MAC MAC mode MAC5 PHY PHY mode PHY4 MAC MAC mode MAC4 PHY PHY mode PHY4 MAC MAC mode MAC4 PHY
1 1 1 1 1 1 1 1 1 1 1 1
MII2 MII PHY mode MAC4 MAC MII MAC mode MAC4 PHY RMII MAC MAC4 Note1
Note1: The port can be connected to an external PHY or MAC device. Note2: All ports are configured as MII/RMII by pin 113 RMII_EN. Each port can be configured as MII/RMII by programming MII register 31.5[10:8]. Note3: RMII_EN takes precedence of P4MII_SNI. Abbreviation: I/F: the type of interface Mode: the port works as a MAC or a PHY Int: the internal block to which the MII port is connected Ext: the external device to which the MII port is connected MAC4: the port 4 of switch engine MAC5: the port 5 of switch engine PHY4: the port 4 of PHY
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To define the speed, duplex and pause of MII port
The speed and duplex of MII port can be configured through pins or registers. IP175C/IP175CH's MII register is not fully compatible to IP175A's. User has to fill MII register 29.31 with 16'h175C before accessing MII registers. The details are shown in the following tables.
MII0 PHY mode (interface to an external MAC, MII registers can be accessed via MDC0, MDIO0) EEPROM MII register Pin Name Reg Name Phy Reg MII0 speed P4_FORCE_100 P4_FORCE_100 20.4 P4_FORCE_100 29 22.10 MII0 duplex MII0 pause P4_FORCE_FULL P4_FORCE_FULL -MAC_X_EN 21.4 4.3 P4_FORCE_FULL MAC_X_EN 29 29 22.5 18.10
MII0 MAC mode (interface to an external PHY), there are two ways to set MII0 speed, duplex and pause. 1. Decided by reading the MII registers 0~5 of external PHY through MDC1, MDIO1. MII0 1. IP175C/IP175CH polls the external PHY with address defined in MII register Speed 31.3[4:0]. The default address value is 00000. Duplex 2. After reset, IP175C/IP175CH writes the speed/duplex/pause capability to the Pause external PHY using the content of MII register 31.3[12:8]. 3. IP175C/IP175CH reads MII register 0~5 of external PHY as MII0 speed, duplex and pause continuously. 2. Force mode (MDC1 and MDIO1 are not connected to external PHY) EEPROM MII register Pin Name Reg Name Phy Reg MII0 speed P4_FORCE_100 P4_FORCE_100 20.4 P4_FORCE_100 29 22.10 MII0 duplex MII0 pause P4_FORCE_FULL P4_FORCE_FULL -MAC_X_EN 21.4 4.3 P4_FORCE_FULL MAC_X_EN 29 29 22.5 18.10
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MII1 PHY mode (interface to an external MAC, MII registers can be accessed via MDC0, MDIO0) The PHY address of MII1 PHY mode is 4. EEPROM MII register Pin Name Reg Name Phy Reg MII1 speed/duplex/ --4 0~5 pause
MII1 MAC mode (interface to an external PHY), there are two ways to set MII1's speed, duplex and pause. 1. IP175C/IP175CH reads the MII registers 0~5 of external PHY through MDC1, MDIO1. MII1 1. IP175C/IP175CH polls the external PHY with address defined in MII register Speed 31.4[4:0]. The default address value is 00001. Duplex 2. After reset, IP175C/IP175CH writes the speed/duplex/pause capability to the Pause external PHY using the content of MII register 31.4[12:8]. 3. IP175C/IP175CH reads MII register 0~5 of external PHY as MII1 speed, duplex and pause continuously. 2. Force mode (MDC1 and MDIO1 are not connected to external PHY) EEPROM MII register Pin Name Reg Name Phy MII1 speed P3_FORCE_100 P3_FORCE_100 20.3 P3_FORCE_100 29 MII1 duplex P3_FORCE_FULL P3_FORCE_FULL 21.3 P3_FORCE_FULL 29 MII1 pause -MAC_X_EN 4.3 MAC_X_EN 29
Reg 22.9 22.4 18.10
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MII2 PHY mode (interface to an external MAC, MII registers can be accessed via MDC0, MDIO0) EEPROM MII register Pin Name Reg Name Phy Reg MII2 speed P3_FORCE_100 P3_FORCE_100 20.3 P3_FORCE_100 29 22.9 MII2 duplex MII2 pause P3_FORCE_FULL P3_FORCE_FULL -MAC_X_EN 21.3 4.3 P3_FORCE_FULL MAC_X_EN 29 29 22.4 18.10
MII2 MAC mode (interface to an external PHY), there are two ways to set MII2 speed, duplex and pause. 1. IP175C/IP175CH reads the MII registers 0~5 of external PHY through MDC1, MDIO1. MII2 1. IP175C/IP175CH polls the external PHY with address defined in MII register Speed 31.4[4:0]. The default address value is 00001. Duplex 2. After reset, IP175C/IP175CH writes the speed/duplex/pause capability to the Pause external PHY using the content of MII register 31.4[12:8]. 3. IP175C/IP175CH reads MII register 0~5 of external PHY as MII2 speed, duplex and pause continuously. 2. Force mode (MDC1 and MDIO1 are not connected to external PHY) EEPROM MII register Pin Name Reg Name Phy MII2 speed P3_FORCE_100 P3_FORCE_100 20.3 P3_FORCE_100 29 MII2 duplex MII2 pause P3_FORCE_FULL P3_FORCE_FULL -MAC_X_EN 21.3 4.3 P3_FORCE_FULL MAC_X_EN 29 29
Reg 22.9 22.4 18.10
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The application circuit of RMII
(P4EXT=1, P4MII_SNI=0, RMII_EN=1) When RMII mode is enabled, IP175C/IP175CH supports reference clock RMII_CLK_OUT for each RMII port. The clock is used by the external PHY (or MAC) and 175C itself. The following circuit diagram is the RMII circuit of MII0.
TXD0_0 TXD0_1 TXEN0 RXD0_0
TXD0 TXD1 TXEN RXD0 RXD1 RXDV REFCLK MDC MDIO
IP175C
RXD0_1 RXDV0
PHY
RMII0_CLK_IN RMII0_CLK_OUT MDC1 MDIO1
The following circuit diagram is the RMII circuit of MII2.
TXD2_0 TXD2_1 TXEN2 RXD2_0
TXD0 TXD1 TXEN RXD0 RXD1 RXDV REFCLK MDC MDIO
IP175C
RXD2_1 RXDV2
PHY
RMII2_CLK_IN RMII2_CLK_OUT MDC1 MDIO1
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The following circuit diagram is the RMII circuit of MII1 MAC mode.
TXD1_0 TXD1_1 TXEN1 RXD1_0
TXD0 TXD1 TXEN RXD0 RXD1 RXDV REFCLK
IP175C
RXD1_1 RXDV1
PHY
RMII_MAC_CLK_IN RMII_MAC_CLK_OUT MDC1 MDIO1
MDC MDIO
The following circuit is the RMII circuit of MII1 PHY mode.
RXD1_0 RXD1_1 RXDV1 TXD1_0 RXD0 RXD1 RXDV TXD0 TXD1 TXEN REFCLK
IP175C
TXD1_1
MAC
TXEN1 RMII1_PHY_CLK_IN RMII_PHY_CLK_OUT MDC0 MDIO0
MDC MDIO
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2.7 SMART MAC
IP175C/IP175CH supports SMART MAC function to solve locked Card's ID issue. The SMART MAC function can be configured to 4LAN+1WAN, 3LAN+2WAN, 2LAN+3WAN or 1LAN+4WAN. The following example illustrates the behavior of IP175C/IP175CH SMART MAC function for 4LAN + 1WAN.
2.7.1
System configuration
The system configuration and its register programming are shown in the following diagram and table.
tag v
untag --
PVID 1,2
MII0 MAC5
CPU
MAC0 PHY0
MAC1 PHY1
MAC2 PHY2
MAC3 PHY3
MAC4 PHY4
4 LAN ports tag -untag v PVID 1 tag --
WAN port untag v PVID 2
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A programming example of SMART MAC example Register Content Description
MII0 doesn't strip the tag of an outgoing packet. MII0 adds a tag to an outgoing packet. Port0~4 strip the tag of an outgoing packet. Port0~4 doesn't add a tag to an outgoing packet. Define PVID of port0~port3 Define PVID of port4 Define PVID of MII0 TAG_VLAN_MASK_1 TAG_VLAN_MASK_2 Define 1 LAN group Enable router function Define VID index as 000 Enable tag VLAN Define port 4 as a WAN port
Tag/ un-tag function setup 29.23[0] 0 29.23[1] 1 29.23[10:6] 11111 29.23[15:11] 00000 PVID function setup 29.24~27 16'h0001 29.28 16'h0002 29.30 16'h0002 VLAN Mask function setup 30.1[13:8] 6'h2f 30.1[5:0] 6'h30 SMART MAC function setup 30.9[2:0] 001 30.9[3] 1 30.9[6:4] 000 30.9[7] 1 30.9[12:8] 10000
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2.7.2 Packet from LAN to WAN
1. PC0 sends a packet to a LAN port with SA equal to PC0 without PVID or PVID equal to 1 2. IP175C/IP175CH forwards the packet to CPU (MII0) with PVID equal to 1. 3. CPU replaces the SA with locked address PC3, replaces PVID with 2 and sends it to IP175C/IP175CH. 4. IP175C/IP175CH forwards the packet to port4 (WAN port).
DA CPU (2) 4 LAN ports (PVID=1) MAC5 (3) DA MAC0 PHY0 (1) (4) DA CPU SA PC0 PVID none or 1 DA WAN SA PC3 PVID none MAC1 PHY1 MAC2 PHY2 MAC3 PHY3 MAC4 PHY4 1 WAN ports (PVID=2) WAN CPU locked SA=PC3 SA PC3 PVID 2 SA PC0 PVID 1
2.7.3
1. 2. 3. 4. 5.
Packet from WAN to LAN
WAN port receives a packet with locked address PC3. IP175C/IP175CH adds a PVID equal to 2 and forwards the packet to CPU (MII0). CPU updates the DA, replaces PVID with 1 and sends it to IP175C/IP175CH. IP175C/IP175CH learns the SA. IP175C/IP175CH forwards the packet to port0 according to the DA.
(4) Learning SA=CPU DA PC0 (3) 4 LAN ports (PVID=1) MAC5 (2) DA MAC0 PHY0 (5) (1) DA PC0 SA CPU PVID none DA PC3 SA WAN PVID none MAC1 PHY1 MAC2 PHY2 MAC3 PHY3 MAC4 PHY4 1 WAN ports (PVID=2) PC3 SA WAN PVID 2 CPU locked SA=PC3 SA CPU PVID 1
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2.8 Built in regulator
IP175C/IP175CH is built in one linear regulator. It use pin 120 REG_OUT to control an external transistor to generator a stable voltage source. IP175C/IP175CH generates a voltage source between 1.70v ~ 2.00v.
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2.9 CoS
IP175C/IP175CH supports two type of CoS. One is port base priority and the other is frame base priority. IP175C/IP175CH supports two levels of priority queues.
2.9.1
Port base priority
The packets received from high priority port will be handled as high priority frames if the port base priority is enabled. It is enabled by programming the "high priority port enable" bit in MII register 29.19~29.21or EEPROM register 14~18. Each port of IP175C/IP175CH can be configured as a high priority port individually.
2.9.2 2.9.2.1
Frame base priority VLAN tag and TCP/IP TOS
IP175C/IP175CH examines the specific bits in VLAN tag and TCP/IP TOS for priority frames if the frame base priority is enabled. A high priority packet will be queued into the high priority queue; this action will ensure more bandwidth is allocated for the high priority packets in the transmission. The packets will be handled as high priority frames if the tag value meets the high priority requirement, that is, priority bits in a VLAN tag bigger than 3 or TCP/IP TOS field not equal to 3'b000. It is enabled by programming the "class of service enable" bit in MII register 29.19~29.21 or EEPROM register 14~18. The frame base priority function of each port can be enabled individually. The ratio of bandwidth of high priority and low priority queue is defined in MII register 30.12[4] or EEPROM 60[4].
VLAN field TCI definition: Bit[15:13]: User Priority 7~0 Bit 12: Canonical Format Indicator (CFI) Bit[11~0]: VLAN ID. IP175C uses bit[15:13] to define priority.
TYPE = 8100 byte 12~13
TCI (tag control information) 14~15
TOS field
IP header definition: Byte 14 Bit[7:0]: IP protocol version number & header length. IP HEADER 14~15 Byte 15: Service type Bit[7~5]: IP Priority (Precedence ) from 7~0 Bit 4: No Delay (D) Bit 3: High Throughput Bit 2: High Reliability (R) Bit[1:0]: Reserved IP175C uses bit[4:2] to define priority.
TYPE = 0800 byte 12~13
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2.9.2.2 IPv4/IPv6 DiffServ
IP175C/IP175CH checks the DiffServ field of a IPv4 frame or Traffic class field [7:2] (TC[7:2]) of a IPv6 frame and uses them to decide the frame's priority if MII register 30.27.0 DIFFSEV_EN is enabled. IP175C/IP175CH uses DiffServ or TC[7:2] as index to select one of 64 bits defined in the MII register 30.28~31 DSCP[63:0]. If the bit is "1", the received frame is handled as a high priority frame.
IPv4 frame format 6 byte Preamble SFD DA 6 byte SA 4 byte 802.1Q tag (optional) 2 byte TYPE=0800 2 byte DATA FCS
VER=0100 4 bit IPv6 frame format 6 byte Preamble SFD DA 6 byte SA 4 byte 802.1Q tag (optional)
Header Size 4 bit
DiffServ 6 bit
RES 2 bit
2 byte TYPE=86DD
2 byte DATA FCS
VER=0110 4 bit
Traffic Class[7:2] 6 bit
RES 2 bit
---4 bit
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2.10 Spanning tree
IP175C/IP175CH supports spanning tree function with the following features: 1. Detect BPDU frames by examining multicast address (01-80-c2-00-00-00). 2. Forward BPDU packets to CPU through MII0 and add special tag for source port information. 3. Forward BPDU packets from CPU according to the special tag in a frame. Please refer to section 2.5 "Tag VLAN / Tag and un-tag function".
2.10.1
Port states
To support spanning tree protocol, each port of IP175C/IP175CH provides five port states shown in the following table. Port 0~4 of IP175C/IP175CH can be configured in one of the five spanning tree states individually by programming MII register 30.16 to enable (disable) forwarding and learning function. Port 5 (MII0) is dedicated for CPU.
State
Disable Blocking Listening Learning Forwarding
Fwd BPDU Fwd BPDU packet packet to CPU from CPU X (note 2) X (note 2) O X (note 3) O O O O O O
Address learning X X X O O
Fwd all packet normally X X X X O
(Forward enable, Learning enable) (0,0) (0,0) (0,0) (0,1) (1,1)
Note1: O: enabled, X: disabled Note2: CPU should not send packets to IP175C/IP175CH and should discard packets from IP175C/IP175CH. Note3: CPU should not send packets to IP175C/IP175CH.
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2.11 Special tag
IP175C/IP175CH supports special tag function to exchange switching information with CPU without involving VLAN tag information. The special tag function is enabled by programming MII register 30.16.7 STAG_EN.
2.11.1
From CPU to switch
When special tag function is enabled, IP175C/IP175CH forwards packets from MII0 (CPU) by checking special tag added by CPU. The tag definition is shown in the following table. IP175C/IP175CH will remove the special tag 81XX and re-calculate CRC when it forwards the packet to a un-tag field. IP175C/IP175CH will update the special tag to 8100 and re-calculate CRC when it forwards the packet to a tag field. Preamble SFD DA SA 81XX(special tag) Data CRC
Special tag 81XX Bit[15:12] 8
bit[11:8] 1
bit[7:5] 3'b0
bit[4:0] 00001: instruct 175C forwards the packet to port 0 00010: instruct 175C forwards the packet to port 1 00100: instruct 175C forwards the packet to port 2 01000: instruct 175C forwards the packet to port 3 10000: instruct 175C forwards the packet to port 4
2.11.2
From switch to CPU
When special tag function is enabled, IP175C/IP175CH sends packets to MII0 (CPU) with source port information by adding special tag to the frame. IP175C/IP175CH will add the special tag 81XX and re-calculate CRC when it receives the packet from a un-tag field. IP175C/IP175CH will update the tag 8100 to 81XX and re-calculate CRC when it receives the packet from a tag field. The tag definition is shown in the following table.
Special tag 81XX Bit[15:12] 8 bit[11:8] 1 bit[7:5] 3'b0 bit[4:0] 00001: the source port of the packet is port 0 00010: the source port of the packet is port 1 00100: the source port of the packet is port 2 01000: the source port of the packet is port 3 10000: the source port of the packet is port 4
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2.12 Static MAC address table
IP175C/IP175CH supports a static MAC address table, which contains two MAC address. When IP175C/IP175CH receives a packet whose destination address matches the pre-defined MAC address in the table, it forwards the packets to a specfic port defined in the MII register 30.26[13:8] static_port_mask_1 and 30.26[5:0] static_port_mask_0. Use can setup the MAC address table and static port mask by programming MII register 30.20~30.26.The static MAC address table has precedence over the dynamic DA look up result. In a spanning tree application, the MII register 30.26[7] static_override_0 is "1", MII register 30.26[6] static_valid_0 is "1", the MII register 30.20~22 MAC address field is 01-80-c2-00-00-00 and the MII register 30.26[5:0] static_port_mask_0 is 6'b100000 (MII0). That is, IP175C/IP175CH will forward BPDU to MII0 (CPU) only in spite of the port states.
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2.13 Serial mode LED
When MII/RMII2 is enabled, there are no enough pins for LED and IP175C/IP175CH sends out LED information through pin 111 SCLK and pin112 SDATA. It is necessary to use TTL chip to decode and drive LED. The application Icircuit is shown below. IP175C/IP175CH supports two types of serial led mode and can be setting by PIN112 or MII register 31.5[1]. The default value is 0 (SERIAL_LED_MODE = 0) and can be setting to 1 by pull up PIN112 (4.7K) or writeing 1 to MII register 31.5[1].
(SERIAL_LED_MODE=1, IP175C/IP175CH supports link, speed, and duplex LED)
VDD
SDATA
A
QA QB
PORT 4 LINK/ACT LED PORT 3 LINK/ACT LED PORT 2 LINK/ACT LED PORT 1 LINK/ACT LED PORT 0 LINK/ACT LED PORT 4 SPEED LED PORT 3 SPEED LED PORT 2 SPEED LED
SCLK
CLK 74HC164 VDD B
QC QD QE QF QG
CLR
QH
VDD
A
QA QB
PORT 1 SPEED LED PORT 0 SPEED LED PORT 4 DUP/COL LED PORT 3 DUP/COL LED PORT 2 DUP/COL LED PORT 1 DUP/COL LED PORT 0 DUP/COL LED
CLK 74HC164 VDD B
QC QD QE QF QG
CLR
QH
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(SERIAL_LED_MODE= 0, IP175C/IP175CH supports link LED only.)
VDD
SDATA
A
QA QB
SCLK
CLK 74HC164 VDD B
QC QD QE QF QG
PORT LED PORT LED PORT LED PORT LED PORT LED
4 LINK/ACT 3 LINK/ACT 2 LINK/ACT 1 LINK/ACT 0 LINK/ACT
CLR
QH
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2.14 LED Blink Timing
LED mode Serial mode update period Active led blink Collision led blink
Link quality fail blink
Blinking speed
22 ms (44ms/2) On -> Off 44ms -> On 176ms -> Off 44ms ... Off -> On 176ms -> Off 44ms ->On 176ms ... On 2s -> Off 2s -> On 2s -> Off 2s ...
Neon like LED(initial setup LED) On 286ms -> Off 2s -> On 286ms -> Off 2s ...
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2.15 Serial management interface
175C supports two serial management interfaces (SMI). User can access IP175C/IP175CH's MII registers through MDC0 and MDIO0. Its format is shown in the following table. To access MII register in IP175C/IP175CH, MDC should be at least one more cycle than MDIO. That is, a complete command consists of 32 bits MDIO data and at least 33 MDC clocks. When the SMI is idle, MDIO is in high impedance. When IP175C/IP175CH interfaces to an external PHY, it uses MDC1 and MDIO1 to read the status of the external PHY.
Frame format

Read <01><10> Operation Write <01><01><10> Operation
MDC
z z
MDIO
1..1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1..1
idle
start code
write
op
A A A A A R R R R R TA b b b b b b b b b b b b b b b b 1111119876543210 4321043210 PHY address = Reg address = 543210 Register data 01h 00h
idle
MDC MDIO
z z z
1..1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 Z 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1..1
idle
start code
read
op
A A A A A R R R R R TA b b b b b b b b b b b b b b b b 1111119876543210 4321043210 PHY address = Reg address = 543210 Register data 01h 00h
idle
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The application of SMI
MDC0 MDIO0
MDC MDIO MDC MDIO
MAC 1
MAC 2
IP175C
Only one MAC is allowed to access the MDC0,MDIO0.
MDC1 MDIO1
MDC MDIO
PHY1
MDC MDIO
PHY2
All PHY can be accessed via the MDC1,MDIO1.
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Data Sheet
2.16 Force mode of PHY
0 X X NWAY 100/Full 100/Full 1 1 1 100/Full 100/Full 100/Half 1 1 0 100/Half 100/Half 100/Half 1 0 1 10/Full 10/Full 10/Half 1 0 0 10/Half 10/Half 10/Half Px_FORCE Px_FORCE_100 Px_FORCE_FULL IP175C/IP175CH's capability IP175C/IP175CH's link result Link partner's (Nway enabled with all capability) link result
Note: Px_FORCE, Px_FORCE_100,and Px_FORCE_full are force mode configuration pins. X is port number. It is from 0 to 4.
2.17
Reset
The IP175C/IP175CH supports three kinds of reset function.
1. Hardware Reset: Pin 93 RESETB should be asserted LOW at least for 5ms to reset IP175C/IP175CH. The IP175C/IP175CH gets initial values from pins and 24C01A EEPROM after reset. 2. Software Reset: After Hardware Reset, user can write 16'h175C to PHY 30 Register 0 via SMI to reset IP175C/IP175CH. The IP175C/IP175CH resets all of PHYs and Switch Engine, but IP175C/IP175CH does not load initial values from pins and 24C01A EEPROM.
4. PHY Reset: Please write "1" to bit 15 of MII register 0 to reset the PHY. The PHY address is from 0 to 4 for port 0~4 respectively.
2.18
Bandwidth control
IP175C/IP175CH provides the bandwidth control mechanism to manage or control the data rate on a limited bandwidth network. By controlling the ingress data rate and the egress data rate, it provides a bandwidth management solution for local area networks and also provides quick and easy allocation of uplink or downlink speeds to meet and guarantee a wide range of customer bandwidth requirements. IP175C/IP175CH provides the easiest way to allocate bandwidth for each port, which defined in MII registers 31.2 ~ 31.0 or EEPROM registers 95 ~ 90. The ingress/egress data rate control range is from 128 kbps to 8 Mbps for each port.
2.19
Fiber mode of port 4 (for IP175CH only)
When FXSD4 is pulled high, port 4 will be 100Mbps fiber mode.There are two kinds of methods to set full duplex or half duplex. 1. Setting from Pin or EEPROM P4EXT: 0. Duplex mode P4_FORCE P4_FORCE_100 P4_FORCE_FULL Full duplex 1 1 1 Half duplex 1 1 0 P4EXT: 1 Duplex mode Full duplex
P4_FORCE P4_FORCE_100 X X Please set half duplex from MDC/MDIO.
P4_FORCE_FULL X
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
2. Setting from MDC/MDIO Duplex mode MII register Full duplex PHY 4 MII register 0 bit 8 Half duplex PHY 4 MII register 0 bit 8
Setting value 1 0
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Data Sheet
2.20 MII registers of PHY
Description
Control Register Status Register PHY Identifier 1 Register PHY Identifier 2 Register Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Registers
Register 0 1 2 3 4 5 6
Default
Note X5 X5 X1 X1 X5 X5 X5
X1: 5 ports share the register X5: Each port has its individual register
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Register descriptions R/W = Read/Write, SC = Self-Clearing, RO = Read Only, LL = Latching Low, LH = Latching High
MII register 0 of PHY0~4 (Each PHY has its own MII register 0 with different PHY address) PHY MII ROM Control register 4~0 0.15 -R/W Description Default
0
4~0
0.14
--
RW/ Reset SC The PHY is reset if user write "1" to this bit. The reset period is around 2ms. User has to wait for at least 2ms to access IP175C/IP175CH. R/W Loop back 1 = Loop back mode 0 = normal operation When this bit set, IP175C/IP175CH will be isolated from the network media, that is, the assertion of TXEN at the MII will not transmit data on the network. All MII transmission data will be returned to MII receive data path in response to the assertion of TXEN. Bit 0.12 is cleared automatically, if this bit is set. User has to program bit 0.12 again after loop back test. RW Speed Selection 1 = 100Mbps 0 = 10Mbps It is valid only if bit 0.12 is set to be 0. RW Auto-Negotiation Enable 1 = Auto-Negotiation Enable 0 = Auto-Negotiation Disable R/W Power Down 1: power down mode 0: normal operation Isolate IP175C/IP175CH doesn't support this function. RW Restart Auto- Negotiation SC 1 = re-starting Auto-Negotiation 0 = Auto-Negotiation re-start complete Setting this bit to logic high will cause IP175C/IP175CH to restart an Auto-Negotiation cycle, but depending on the value of bit 0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then this bit has no effect, and it is Read Only. This bit is self-clearing after Auto-Negotiation process is completed. R/W Duplex mode 1 = full duplex 0 = half duplex It is valid only if bit 0.12 is set to be 0. R/W Collision test RO Reserved
0
4~0
0.13
--
1
4~0
0.12
--
1
4~0
0.11
--
0
4~0 4~0
0.10 0.9
---
0 0
4~0
0.8
--
0
4~0 4~0
0.7 0[6:0]
---
0 0
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Data Sheet
MII register 1 of PHY0~4 (Each PHY has its own MII register 1 with different PHY address) PHY MII ROM Status register 4~0 1.15 -R/W Description Default
0
RO 100Base-T4 capable 1 = 100Base-T4 capable 0 = not 100Base-T4 capable IP175C/IP175CH does not support 100Base-T4. This bit is fixed to be 0. RO 100Base-X full duplex Capable 1 = 100Base-X full duplex capable 0 = not 100Base-X full duplex capable RO 100Base-X half duplex Capable 1 = 100Base-X half duplex capable 0 = not 100Base-X half duplex capable RO 10Base-T full duplex Capable 1 = 10Base-T full duplex capable 0 = not 10Base-T full duplex capable RO 10Base-T half duplex Capable 1 = 10Base-T half duplex capable 0 = not 10Base-T half duplex capable RO Reserved RO MF preamble Suppression 1 = preamble may be suppressed 0 = preamble always required RO Auto-Negotiation Complete 1 = Auto-Negotiation complete 0 = Auto-Negotiation in progress When read as logic 1, indicates that the Auto-Negotiation process has been completed, and the contents of register 4 and 5 are valid. When read as logic 0, indicates that the Auto-Negotiation process has not been completed, and the contents of register 4 and 5 are meaningless. If Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this bit will always read as logic 0. RO Remote fault LH 1 = remote fault detected 0 = not remote fault detected When read as logic 1, indicates that IP175C/IP175CH has detected a remote fault condition. This bit is set until remote fault condition gone and before reading the contents of the register. This bit is cleared after IP175C/IP175CH reset. RO Auto-Negotiation Ability 1 = Auto-Negotiation capable 0 = not Auto-Negotiation capable When read as logic 1, indicates that IP175C/IP175CH has the ability to perform Auto-Negotiation.
4~0
1.14
--
1
4~0
1.13
--
1
4~0
1.12
--
1
4~0
1.11
--
1
4~0 4~0
1[10:7] 1.6
---
0 1
4~0
1.5
--
0
4~0
1.4
--
0
4~0
1.3
--
1
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII register 1 of PHY0~4 (Each PHY has its own MII register 1 with different PHY address) PHY MII ROM
--
R/W
Description
Default
0
Status register 4~0 1.2
RO Link Status LL 1 = Link Pass 0 = Link Fail When read as logic 1, indicates that IP175C/IP175CH has determined a valid link has been established. When read as logic 0, indicates the link is not valid. This bit is cleared until a valid link has been established and before reading the contents of this registers. Jabber Detect 1 = jabber condition detected 0 = no jabber condition detected When read as logic 1, indicates that IP175C/IP175CH has detected a jabber condition. This bit is always 0 for 100Mbps operation and is cleared after IP175C/IP175CH reset. When the duration of TXEN exceeds the jabber timer (21ms), the transmission and loop back functions will be disabled and the COL is active. After TXEN goes low for more than 500 ms, the transmitter will be re-enabled. RO Extended capability 1 = Extended register capabilities 0 = No extended register capabilities IP175C/IP175CH has extended register capabilities.
4~0
1.1
--
0
4~0
1.0
--
1
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII register 2 of PHY0~4 (5 PHYs share the MII register) PHY MII ROM R/W Description Default PHY Identifier 1 register 4~0 2 -RO IP175C/IP175CH OUI (Organizationally Unique Identifier) ID, 16'h0243 the msb is 3rd bit of IP175C/IP175CH OUI ID, and the lsb is 18th bit of IP175C/IP175CH OUI ID. IP175C/IP175CH OUI is 0090C3.
MII register 3 of PHY0~4 (5 PHYs share the MII register) PHY MII ROM R/W Description PHY Identifier 2 register 4~0 3[15:10] -RO PHY identifier IP175C/IP175CH OUI ID, the msb IP175C/IP175CH OUI ID, and lsb IP175C/IP175CH OUI ID. 4~0 3[9:4] -RO Manufacture's Model Number IP175C/IP175CH model number 4~0 3[3:0] -RO Revision Number IP175C/IP175CH revision number Default
6'h03 bit bit of of 6'h18 0
is is
19th 24th
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII register 4 of PHY0~4 (Each PHY has its own MII register 4 with different PHY address) PHY MII ROM R/W Description Auto-Negotiation Advertisement register 4~0 4.15 -RO Next Page Not supported. This bit is fixed to be 0. 4~0 4.14 -RO Reserved by IEEE, write as 0, ignore on read 4~0 4.13 -R/W Remote Fault 1: Advertises that this port has detected a remote fault. 0: There is no remote fault. 4~0 4[12:11] -RO Reserved for future IEEE use, write as 0, ignore on read 4~0 4.10 -RW Pause 1 = Advertises that this port has implemented pause function 0 = No pause function supported 4~0 4.9 -RO 100BASE-T4 Not supported 4~0 4.8 -R/W 100BASE-TX full duplex 1 = 100BASE-TX full duplex is supported 0 = 100BASE-TX full duplex is not supported FORCE FORCE100 FORCE FULL Default 0 Don't care Don't care 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 4~0 4.7 -R/W 100BASE-TX 1 = 100BASE-TX is supported 0 = 100BASE-TX is not supported FORCE FORCE100 FORCE FULL Default 0 Don't care Don't care 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 4~0 4.6 -R/W 10BASE-T full duplex 1 = 10BASE-T full duplex is supported 0 = 10BASE-T full duplex is not supported FORCE FORCE100 FORCE FULL Default 0 Don't care Don't care 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 4~0 4.5 -R/W 10BASE-T 1 = 10BASE-T is supported 0 = 10BASE-T is not supported 4~0 4[4:0] -RO Selector Field Use to identify the type of message being sent by Auto-Negotiation.
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Default
0 0 0
0 Set by X_EN 0 *
*
*
1
5'b00001
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII register 5 of PHY0~4 (Each PHY has its own MII register 5 with different PHY address) PHY MII ROM R/W Description Default Auto-Negotiation Link Partner Ability register 4~0 5.15 RO Next Page 0 1 = Next Page ability is supported by link partner 0 = Next Page ability does not supported by link partner 4~0 5.14 RO Acknowledge 0 1 = Link partner has received the ability data word 0 = Not acknowledge 4~0 5.13 RO Remote Fault 0 1 = Link partner indicates a remote fault 0 = No remote fault indicate by link partner If this bit is set to logic 1, then bit 1.4 (Remote fault) will set to logic 1. 4~0 5[12:11] -RO Reserved by IEEE for future use, write as 0, read as 0. 0 4~0 5.10 -RW Pause 0 1 = Link partner support IEEE802.3x 0 = Link partner does not support IEEE802.3x When Nway enabled, this bit reflects link partner ability. (read only) When Nway disabled, this bit can be set by SMI. (read/write) When in 100FX, this bit is set by X_EN or SMI. 4~0 5.9 -RO 100BASE-T4 0 1 = Link partner support 100BASE-T4 0 = Link partner does not support 100BASE-T4 4~0 5.8 -RO 100BASE-TX full duplex 0 1 = Link partner support 100BASE-TX full duplex 0 = Link partner does not support 100BASE-TX full duplex 4~0 5.7 -RO 100BASE-TX 0 1 = Link partner support 100BASE-TX 0 = Link partner does not support 100BASE-TX For 100FX mode, this bit is set. When Nway is disabled, this bit is set if register 0.13=1. 4~0 5.6 -RO 10BASE-T full duplex 0 1 = Link partner support 10BASE-T full duplex 0 = Link partner does not support 10BASE-T full duplex 4~0 5.5 -RO 10BASE-T 0 1 = Link partner support 10BASE-T 0 = Link partner does not support 10BASE-T When Nway is disabled, this bit is set if register 0.13=0 4~0 5[4:0] -RO Selector Field 5'b000 Protocol selector of the link partner 00
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII register 6 of PHY0~4 (Each PHY has its own MII register 6 with different PHY address) PHY MII ROM R/W Description Default Auto-Negotiation Expansion register 4~0 6[15:5] -RO Reserved 0 4~0 6.4 -RO 1: a fault has been detected via parallel detection function. 0 0: a fault has not been detected via parallel detection function. 4~0 6.3 -RO 1= Link partner is next page able. 0 0= Link partner is not next page able. 4~0 6.2 -RO 1: IP175C/IP175CH next page able. 0 0: IP175C/IP175CH is not next page able. This bit is fixed to be "0" in IP175C/IP175CH 4~0 6.1 -RO/ 1: A new page has been received. 0 LH 0: A new page has not been received. 4~0 6.0 -RO If Nway is enabled, this bit means: 0 1: Link partner is Auto-Negotiation able. (Nway) 0: Link partner is not Auto-Negotiation able. (100FX) In 100FX or Nway disabled, this bit always =0.
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
2.21
PHY 29
MII registers of Switch controller
MII 18.15 18.14 ROM 2.1 2.0 R/W Description R/W LED_SEL [1:0] LED mode selection. LED_SEL[1:0]=2'b00: LED mode 0, LED_SEL[1:0]=2'b01: LED mode 1, LED_SEL[1:0]=2'b10: LED mode 2, LED_SEL[1:0]=2'b11: LED mode 3 (default)
It is for debug only. User should not update the setting of LED_SEL pins by writing this registers.
Default Pin92, Pin91
29
18.13
4.7
R/W X_EN IEEE 802.3x flow control enable This signal is used as pause_en for digital parts. 1: enable (default), 0:disable Default value TEST2=0 Pin113 MII2_EN=1 Pin113 MII2_EN=0 1 Pin100 X_EN (1) 1 TEST2=1
*
29
18.12
4.4
R/W BK_EN, Backpressure enable 1: enable (default), 0: disable Default value TEST2=0 Pin113 MII2_EN=1 Pin113 MII2_EN=0 1 Pin100 X_EN (1) TEST2=1 1
*
29
18.11
4.2
R/W BF_STM_EN, Broadcast storm enable 1: enable Drop the incoming packet if the number of queued broadcast packet is over the threshold. The threshold is defined in MII register 30.11[15:14]. 0: disable (default) Default value TEST2=0 Pin113=1 0 Pin113 MII2_EN=0 LAT_IN_DIS=1 Pin102 BF_STM_EN (0) LAT_IN_DIS=0 0 0 TEST2=1
*
29
18.10
4.3
R/W MAC_X_EN, flow control enable of MII0 and MII2 1: enable (default), 0: disable Default value TEST2=0 Pin74 P4EXT=1 1 Pin74 P4EXT =0 Pin67 MAC_X_EN (1) 0 TEST2=1
*
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29
29
MII 18.5
18.4
ROM 6.7
6.5
29
18.3
6.4
R/W Description Default R/W Reserved 0 The default value must be adopted for normal operation. R/W HASH_MODE 0 It is latched as Hashing algorithm selection for 1st layer and 2nd layer at the end of reset. 0: direct and CRC (default) 1: direct and CRC R/W AGING * Aging time of address table selection An address tag in hashing table will be dropped if this function is turned on and its aging timer expires. Aging =bit[4] 0: no aging 1: aging time is around 280 sec (default) Default value TEST2=0 TEST2=1 Pin74 P4EXT=1 Pin74 P4EXT=0 1 Pin65 AGING (1) 1
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 19.15 ROM 14.7 R/W Description Default R/W Port0 VLAN look up table * Port5 and port0 are in the same VLAN Default value Testmode38, 39 Others 0 1 R/W Port0 Class of service enable * 1: enable, 0: disabled (default) Packets with high priority tag from port0 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin63 COS_EN (0) 0 R/W Port0 high priority port enable 1'b0 1: enable, 0: disabled (default) Packets received from port0 are handled as high priority packets. R/W Port0 VLAN look up table *
The register defines the ports in the same VLAN as port0. The bit 0~4 are corresponding to port 0~4. 1: a port is in the same VLAN as port0 0: a port is not in the same VLAN as port0 Bit8, don't care; Bit9=1, port 1 and port0 are in the same VLAN; Bit10=1, port 2 and port0 are in the same VLAN; Bit11=1, port 3 and port0 are in the same VLAN; Bit12=1, port 4 and port0 are in the same VLAN Default value Testmode38, 39 5'b00111 Testmode47 5'b00001 Others 5'b11111
19.14
14.6
19.13
14.5
19[12.8] 14[4:0]
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 19.7 ROM 15.7 R/W Description Default R/W Port1 VLAN look up table * Port5 and port1 are in the same VLAN Default value Testmode38, 39 Others 0 1 R/W Port1 Class of service enable * 1: enable, 0: disabled (default) Packets with high priority tag from port1 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin63 COS_EN (0) 0 R/W Port1 high priority port enable 1'b0 1: enable, 0: disabled (default) Packets received from port1 are handled as high priority packets. R/W Port1 VLAN look up table *
The register defines the ports in the same VLAN as port1. The bit 0~4 are corresponding to port 0~4. 1: a port is in the same VLAN as port1 0: a port is not in the same VLAN as port1 Bit0=1, port 0 and port1 are in the same VLAN; Bit1, don't care; Bit2=1, port 2 and port1 are in the same VLAN; Bit3=1, port 3 and port1 are in the same VLAN; Bit4=1, port 4 and port1 are in the same VLAN Default value Testmode38, 39
5'b01110
19.6
15.6
19.5
15.5
19[4:0]
15[4:0]
Testmode47
5'b00010
Others
5'b11111
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 20.15 ROM 16.7 R/W Description Default R/W Port2 VLAN look up table * Port5 and port2 are in the same VLAN Default value Testmode38, 39 Others 0 1 R/W Port2 Class of service enable * 1: enable, 0: disabled (default) Packets with high priority tag from port2 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin63 COS_EN (0) 0 R/W Port2 high priority port enable 1'b0 1: enable, 0: disabled (default) Packets received from port2 are handled as high priority packets. R/W Port2 VLAN look up table *
The register defines the ports in the same VLAN as port2. The bit 0~4 are corresponding to port 0~4. 1: a port is in the same VLAN as port2 0: a port is not in the same VLAN as port2 Bit8=1, port 0 and port2 are in the same VLAN; Bit9=1, port 1 and port2 are in the same VLAN; Bit10=1, don't care; Bit11=1, port 3 and port2 are in the same VLAN; Bit12=1, port 4 and port2 are in the same VLAN Default value Testmode38, 39 Testmode47 Others 5'b11100 5'b00100 5'b11111
20.14
16.6
20.13
16.5
20[12:8] 16[4:0]
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 20.7 ROM 17.7 R/W Description R/W Port3 VLAN look up table
Port5 and port3 are in the same VLAN R/W Port3 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from port3 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin63 COS_EN (0) 0 R/W Port3 high priority port enable 1: enable, 0: disabled (default) Packets received from port3 are handled as high priority packets. R/W Port3 VLAN look up table The register defines the ports in the same VLAN as port3. The bit 0~5 are corresponding to port 0~5. 1: a port is in the same VLAN as port3 0: a port is not in the same VLAN as port3 Bit0=1, port 0 and port3 are in the same VLAN; Bit1=1, port 1 and port3 are in the same VLAN; Bit2=1, port 2 and port3 are in the same VLAN; Bit3=1, don't care; Bit4=1, port 4 and port3 are in the same VLAN Default value Testmode38, 39 Testmode47 Others 5'b11000 5'b01000 5'b11111
Default 1'b1
20.6
17.6
*
20.5
17.5
1'b0
20[4:0]
17[4:0]
*
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IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 21.15
21.14
ROM 18.7
18.6
21.13
18.5
21[12:8] 18[4:0]
R/W Description Default R/W Port4 VLAN look up table 1'b1 Port5 and port4 are in the same VLAN R/W Port4 Class of service enable * 1: enable, 0: disabled (default) Packets with high priority tag from port4 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin63 COS_EN (0) 0 R/W Port4 high priority port enable * 1: enable, 0: disabled (default) Packets received from port4 are handled as high priority packets. Default value TEST2=0 TEST2=1 P4EXT=1 P4EXT=0 0 Pin 64 P4_HIGH (0) 0 R/W Port4 VLAN look up table *
The register defines the ports in the same VLAN as port4. The bit 0~5 are corresponding to port 0~5. 1: a port is in the same VLAN as port4 0: a port is not in the same VLAN as port4 Bit8=1, port 0 and port4 are in the same VLAN; Bit9=1, port 1 and port4 are in the same VLAN; Bit10=1, port 2 and port4 are in the same VLAN; Bit11=1, port 3 and port4 are in the same VLAN; Bit12=1, don't care; Default value Testmode38, 39 5'b10001 Testmode47 5'b10000 Others 5'b11111
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 22.15 ROM 19.4 R/W Description R/W P4_FORCE Port4 force mode enable 1: enable force mode 0: disable force mode, port4 NWAY with all capability Default value P4EXT=1 P4EXT=0 Pin 96 Pin 96 MII0_MAC_MOD=1 MII0_MAC_MOD=0 0 Pin76 Pin85 R/W P3_FORCE Port3 force mode enable 1: enable force mode 0: disable force mode, port3 NWAY with all capability Default value P4EXT=1 P4EXT=0 MII0_MAC_MOD=1 MII0_MAC_MOD=0 0 Pin77 Pin86 R/W P2_FORCE Port2 force mode enable 1: enable force mode 0: disable force mode, port2 NWAY with all capability Default value P4EXT=1 P4EXT=0 MII0_MAC_MOD=1 MII0_MAC_MOD=0 0 Pin78 (0) Pin87 (0) R/W P1_FORCE Port1 force mode enable 1: enable force mode 0: disable force mode, port1 NWAY with all capability Default value P4EXT=1 P4EXT=0 MII0_MAC_MOD=1 MII0_MAC_MOD=0 0 Pin79 (0) Pin88 (0) R/W P0_FORCE Port0 force mode enable 1: enable force mode 0: disable force mode, port0 NWAY with all capability Default value P4EXT=1 P4EXT=0 Pin 96 Pin 96 MII0_MAC_MOD=1 MII0_MAC_MOD=0 0 Pin80 (0) Pin90 (0) Default *
29
22.14
19.3
*
29
22.13
19.2
*
29
22.12
19.1
*
29
22.11
19.0
*
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 MII 22.10 ROM 20.4 R/W Description R/W P4_FORCE100 It is valid only if p4_force (22[15]) is set to 1'b1. Default value Pin 113 MII2_EN=1 Pin 113 MII2_EN=0 0 Pin103 (0) P4EXT=1 1: force MII0 (PHY mode) to be 100M 0: force MII0 (PHY mode) to be 10M R/W P3_FORCE100 Force port3 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p3_force (22[14]) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 Pad 98.5 Pad 98.5 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin104 (0) P4EXT=1 1: force MII2 (PHY mode) to be 100M 0: force MII2 (PHY mode) to be 10M R/W P2_FORCE100 Force port2 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p2_force (22[13]) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin105 (0) R/W P1_FORCE100 Force port1 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p1_force (22[12]) is set to 1'b1. Default Pin 113 MII2_EN=1 Pin 113 MII2_EN=0 0 Pin106 (0) R/W P0_FORCE100 Force port0 to be 100M 1: force to be 100M 0: force to be 10M It is valid only if p0_force (22[11]) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin107 (0)
74/111 Copyright (c) 2004, IC Plus Corp.
Default *
P4EXT=0 1: force port4 to be 100M 0: force port4 to be 10M 29 22.9 20.3
*
P4EXT=0 1: force port3 to be 100M 0: force port3 to be 10M 29 22.8 20.2
*
29
22.7
20.1
*
29
22.6
20.0
*
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 29 R/W Description R/W P4_FORCE_FULL It is valid only if p4_force (22.15) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 Pad 98.5 Pad 98.5 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin108 (0) P4EXT=0 P4EXT=1 1: force port4 to be full duplex 1: force MII0 (PHY mode) to be full duplex 0: force port4 to be half duplex 0: force MII0 (PHY mode) to be half duplex 29 22.4 21.3 R/W P3_FORCE_FULL Force port3 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (22.14) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 0 Pin109 (0) P4EXT=0 P4EXT=1 1: force port3 to be full duplex 1: force MII2 (PHY mode) to be full duplex 0: force port3 to be half duplex 0: force MII2 (PHY mode) to be half duplex 29 22.3 21.2 R/W P2_FORCE_FULL Force port2 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (22.13) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 Pad 98.5 Pad 98.5 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin110 (0) 29 22.2 21.1 R/W P1_FORCE_FULL Force port1 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (22.12) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 Pad 98.5 Pad 98.5 LAT_IN_DIS=1 LAT_IN_DIS=0 0 0 Pin111 (0) 29 22.1 21.0 R/W P0_FORCE_FULL Force port0 to be full duplex 1: force full duplex 0: force half duplex It is valid only if p4_force (22.11) is set to 1'b1. Default MII2_EN=1 Pin 113 MII2_EN=0 0 Pin112 (0)
75/111 Copyright (c) 2004, IC Plus Corp.
MII 22.5
ROM 21.4
Default *
*
*
*
*
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Tag register 10 PHY MII ROM 29 23[15:11] 22[4:0] R/W Description Default R/W ADD_TAG. Add VLAN tag 5'h00 Portx adds a VLAN tag defined in vlan_tag_x to each outgoing packet Bit 11 1: port0 adds a VLAN tag to each outgoing packet. 0: port0 doesn't add a VLAN tag. Bit 12 1: port1 adds a VLAN tag to each outgoing packet. 0: port1 doesn't add a VLAN tag. Bit 13 1: port2 adds a VLAN tag to each outgoing packet. 0: port2 doesn't add a VLAN tag. Bit 14 1: port3 adds a VLAN tag to each outgoing packet. 0: port3 doesn't add a VLAN tag. Bit 15 1: port4 adds a VLAN tag to each outgoing packet. 0: port4 doesn't add a VLAN tag.
76/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Tag register 11 PHY MII ROM 29 23[10:6] 23[4:0] R/W Description R/W REMOVE_TAG. Remove VLAN tag 1: port0 removes the VLAN tag of each outgoing packet. Bit 6
0: port0 doesn't remove the VLAN tag of each outgoing packet.
Default 5'h00
Bit 7 Bit 8 Bit 9 Bit 10
1: port1 removes the VLAN tag of each outgoing packet. 0: port1 doesn't remove the VLAN tag of each outgoing packet. 1: port2 removes the VLAN tag of each outgoing packet. 0: port2 doesn't remove the VLAN tag of each outgoing packet. 1: port3 removes the VLAN tag of each outgoing packet. 0: port3 doesn't remove the VLAN tag of each outgoing packet. 1: port4 removes the VLAN tag of each outgoing packet. 0: port4 doesn't remove the VLAN tag of each outgoing packet.
Default value Others 5'b00000 23.1 22.5 Testmode37 5'b11111 *
R/W ADD_TAG. Add VLAN tag 1: Port5 adds a VLAN tag to each outgoing packet. 0: Port5 doesn't add a VLAN tag. Default value Others 0 Testmode37 1
23.0
23.5
R/W REMOVE_TAG. Remove VLAN tag 1: Port5 removes the VLAN tag of each outgoing packet. 0: port5 doesn't remove the VLAN tag of each outgoing packet.
1'b0
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Tag register 1~9 PHY 29 MII 24 ROM 25[7:0] 24[7:0]
27[7:0] 26[7:0] 29[7:0] 28[7:0] 31[7:0] 30[7:0] 33[7:0] 32[7:0]
29
25
29
26
29
27
29
28
R/W Description R/W VLAN_TAG_0. Port0 default VLAN tag value This register defines the VLAN tag added packet from port 0. R/W VLAN_TAG_1. Port1 default VLAN tag value This register defines the VLAN tag added packet from port 1. VLAN_TAG_2. Port2 default VLAN tag value This register defines the VLAN tag added packet from port 2. R/W VLAN_TAG_3. Port3 default VLAN tag value This register defines the VLAN tag added packet from port 3. R/W VLAN_TAG_4. Port4 default VALN tag value This register defines the VLAN tag added packet from port 4.
Default
16'h0001 to an un-tagged 16'h0001 to an un-tagged 16'h0001 to an un-tagged 16'h0001 to an un-tagged 16'h0002 to an un-tagged
78/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY MII ROM 29 29[15:8] 36[7:0] 29 29[7:0] 35[7:0] R/W R/W REG29SW- reserved R/W REG29SW- reserved Description Default 8'h01 8'h00
PHY 29
MII 30
ROM 38[7:0] 37[7:0]
R/W Description Default R/W VLAN_TAG_5. Port5 default VALN tag value 16'h0002 This register defines the VLAN tag of an un-tagged packet from port 5.
IP175C/IP175CH enable register PHY 29 MII 31 ROM -R/W Description R/W IP175C/IP175CH register enable register
IP175C/IP175CH MII register don't support IP175A compatible mode. If the value of this register is 16'h175A, please fill this register with 16'h175C. Note1: The default value is 16'h175A if p4ext is 1, MII1_dis is, 0 and mii1_phy_mod is 1; otherwise the default value is 16'h175C.
Default Note1
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 MII 0 ROM
--
R/W Description Default R/W Software reset register 16'h00 IP175C/IP175CH is reset if uses write "175C"to this register. It is self-cleared. The reset period is around 2ms. User has to wait for at least 2ms to access IP175C/IP175CH. MII registers 29.x, 30.x, 31.x are not reset by software reset.
80/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Tag VLAN register 2 PHY 30 MII 1[5:0] ROM 39[5:0] R/W Description R/W TAG_VLAN_MASK_0[5:0]. Tag VLAN 0 output port mask
The mask is valid only if MII register 9.7 TAG_VLAN_EN is logic high and VID index is 4'b0000. When IP175C/IP175CH receives a packet, it examines the VID index to choose a tag VLAN mask and forwards the packets according MAC address table and the mask. Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 1: port 0 belongs to VLAN 0 0: port 0 doesn't belong to VLAN 0 1: port 1 belongs to VLAN 0 0: port 1 doesn't belong to VLAN 0 1: port 2 belongs to VLAN 0 0: port 2 doesn't belong to VLAN 0 1: port 3 belongs to VLAN 0 0: port 3 doesn't belong to VLAN 0 1: port 4 belongs to VLAN 0 0: port 4 doesn't belong to VLAN 0 1: port 5 belongs to VLAN 0 0: port 5 doesn't belong to VLAN 0
Default 6'h3f
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Tag VLAN register 3~17 PHY 30 MII 1[13:8] 2[13:8] 2[5:0] 3[13:8] 3[5:0] 4[13:8] 4[5:0] 5[13:8] 5[5:0] 6[13:8] 6[5:0] 7[13:8] 7[5:0] 8[13:8] 8[5:0] ROM 40[5:0] 42[5:0] 41[5:0] 44[5:0] 43[5:0] 46[5:0] 45[5:0] 48[5:0] 47[5:0] 50[5:0] 49[5:0] 52[5:0] 51[5:0] 54[5:0] 53[5:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description TAG_VLAN_MASK_1[5:0]. Tag VLAN 1 output port mask TAG_VLAN_MASK_3[5:0]. Tag VLAN 3 output port mask TAG_VLAN_MASK_2[5:0]. Tag VLAN 2 output port mask TAG_VLAN_MASK_5[5:0]. Tag VLAN 5 output port mask TAG_VLAN_MASK_4[5:0]. Tag VLAN 4 output port mask TAG_VLAN_MASK_7[5:0]. Tag VLAN 7 output port mask TAG_VLAN_MASK_6[5:0]. Tag VLAN 6 output port mask TAG_VLAN_MASK_9[5:0]. Tag VLAN 9 output port mask TAG_VLAN_MASK_8[5:0]. Tag VLAN 8 output port mask TAG_VLAN_MASK_B[5:0]. Tag VLAN b output port mask TAG_VLAN_MASK_A[5:0]. Tag VLAN a output port mask TAG_VLAN_MASK_D[5:0]. Tag VLAN d output port mask TAG_VLAN_MASK_C[5:0]. Tag VLAN c output port mask TAG_VLAN_MASK_F[5:0]. Tag VLAN f output port mask TAG_VLAN_MASK_E[5:0]. Tag VLAN e output port mask Default 6'h2f 6'h3f 6'h30 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f 6'h3f
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Router control register 1 PHY MII 30 9[12:8] ROM 56[4:0] R/W Description R/W WAN_PORTS[4:0]. WAN ports for router application
It is valid only if router_en is enabled. Bit0 1: port 0 is a WAN port 0: port 0 is not a WAN port Bit1 Bit2 Bit3 Bit4 30 9.7 55.7 1: port 1 is a WAN port 0: port 1 is not a WAN port 1: port 2 is a WAN port 0: port 2 is not a WAN port 1: port 3 is a WAN port 0: port 3 is not a WAN port 1: port 4 is a WAN port 0: port 4 is not a WAN port *
Default 5'h10
R/W TAG_VLAN_EN. Enable tag VLAN function 1: enable tag VLAN function 0: disable tag VLAN function Default value Others Testmode37
9[6:4]
55[6:4]
0 1 R/W VID_IDX_SEL. VID index selection 3'b000 Select 4 bits out of 12 bits VID as index of tag VLAN groups. The 12 bits of VID can't be all zeros; otherwise, it will be handled as an un-tagged frame. 000: VID[3:0], 001: VID[4:1], 010: VID[5:2], 011: VID[6:3], 100: VID[7:4], 101: VID[8:5], 110: VID[9:6], 111: VID[10:7] An example of vid_idx_sel = 3'b000, VLAN_0 VID[3:0] = 4'b0000 VLAN_1 VLAN_2 VLAN_3 .... VLAN_e VLAN_f VID[3:0] = 4'b0001 VID[3:0] = 4'b0010 VID[3:0] = 4'b0011 .... VID[3:0] = 4'b1110 VID[3:0] = 4'b1111 *
30
9.3
55.3
R/W ROUTER_EN. Enable router function at MII port 1: SMART MAC enabled. 0: SMART MAC disabled. Default value Others 0 Testmode37 1
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 MII 9[2:0] ROM 55[2:0] R/W R/W LAN_GROUPS[2:0]. Description Default 3'b001
Number of VLAN groups of LAN ports in a router application It defines the VLANs used by LAN ports. Each VLAN should contain MII port. It is valid only if router_en is enabled. 000: unsupported value 001: 1 VLAN group, (VLAN 1) 010: 2 VLAN groups, (VLAN 1~VLAN 2) 011: 3 VLAN groups, (VLAN 1~VLAN 3) 100: 4 VLAN groups, (VLAN 1~VLAN 4) 101: 5 VLAN groups, (VLAN 1~VLAN 5) 110: 6 VLAN groups, (VLAN 1~VLAN 6) 111: 7 VLAN groups, (VLAN 1~VLAN 7)
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Router control register 2 PHY 30 MII 10[5:0] ROM 57[5:0] R/W Description R/W PORT_LOCK_EN[5:0]. Lock port MAC address 1: enable 0: disable
User has to reset IP175C/IP175CH by writing 16'h175C to MII register 30.0 software reset register after enabling this function. Bit0 1: port lock enabled in port 0 0: port lock disabled in port 0 Bit1 Bit2 Bit3 Bit4 Bit5 1: port lock enabled in port 1 0: port lock disabled in port 1 1: port lock enabled in port 2 0: port lock disabled in port 2 1: port lock enabled in port 3 0: port lock disabled in port 3 1: port lock enabled in port 4 0: port lock disabled in port 4 1: port lock enabled in MII port 0: port lock disabled in MII port
Default 6'b0
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Switch control register 3 PHY MII ROM 30 11[15:14] 59[7:6] R/W Description Default R/W BF_STM_THR_SEL[1:0]. 2'b00 Broadcast storm threshold selection 00: 159 packets/10ms for 100Mbps port, or 159 packets/100ms for 10Mbps port, 01: 127 packets/10ms for 100Mbps port, or 127 packets/100ms for 10Mbps port, 10: 63 packets/10ms for 100Mbps port, or 63 packets/100ms for 10Mbps port, 11: 31 packets/10ms for 100Mbps port, or 31 packets/100ms for 10Mbps port, R/W The default value should be adopted for normal operation. 2'b00 R/W The default value should be adopted for normal operation. 2'b00 R/W UNIT_LOW_THR_SEL[1:0] 2'b00 The default value should be adopted for normal operation. R/W UNIT_HIGH_THR_SEL[1;0]. 2'b00 The default value should be adopted for normal operation. R/W BF_STM_EN_QM 1'b0 The default value should be adopted for normal operation. R/W PREDROP_EN 1'b0 1: Drop an incoming broadcast packet if any port is congested. 0: forward an incoming broadcast packet to un-congested ports instead of congested ports. R/W PKT_LOW_THR_SEL[1:0]. 2'b00 The default value should be adopted for normal operation. R/W PKT_HIGH_THR_SEL[1:0]. 2'b00 The default value should be adopted for normal operation.
11[13:12] 59[5:4] 11[11:10] 59[3:2] 11[9:8] 11[7:6] 11.5 11.4 59[1:0] 58[7:6] 58.5 58.4
11[3:2] 11[1:0]
58[3:2] 58[1:0]
86/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 MII 12.8 ROM 4.6 R/W Description Default R/W BW_EN_QM 1'b1 Limitation for output queue quantity when TX Bandwidth control enable 1: enable (default), limit the output queue quantity 2: disable, unlimit the output queue quantity
R/W LINK_Q_EN, LINK quality enable 1: enable (default), 0: disable Default value TEST2=0 Pad 98.5 LAT_IN_DIS=1 1 12.5 60.5 Pad 98.5 LAT_IN_DIS=0 Pin101 (1) 1 * TEST2=1 *
12.7
60.7
R/W LONG_PACKET Max forwarded packet length 1: 1552 bytes 0: 1536 bytes (default) P4EXT=1 0 Default value P4EXT=0 Pin66 LONG_PKT (0)
12.4
60.4
R/W PRIORITY_RATE 1: 8 packets 0: 4 packets Output Queue Scheduling: high priority packet rate R/W Reserved (Must to be keep at 1'b1) R/W HP_DIS_FLOW_EN High priority packet to disable flow control 1: a port will disable its flow control function for 2 sec if it receives a high priority packet. 0: the function is disabled
1'b0
12.1 12.0
60.1 60.0
1'b1 1'b0
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY MII 30 13[3:0] ROM 96[3:0] R/W Description Default R/W RESERVED_ADD_FORWARD[3:0] * BIT3 Reserved MAC address (0180C2000010-0180C20000FF) 1: forward (default), 0: discard. BIT2 Reserved MAC address (0180C2000002- 0180C200000F) 1: forward (default), 0: discard. The default value is the inverted value of pin 69 FILTER_RSV_DA. BIT1 Reserved MAC address (0180C2000001) 1: forward, 0: discard (default) BIT0 Reserved MAC address (0180C2000000) 1: forward (default), 0: discard Default value P4EXT=1 P4EXT=0 1101 {1, inv of pin69 FILTER_RSV_DA(0), 0, 1}
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
Spanning tree register PHY 30 MII 16.15 ROM -R/W Description Default * RO Fast mode for simulation, 1: Fast mode, 0: normal mode Default value TEST2=0 TEST2=1 0 Pin 66 FASTMODE (0) R/W Learning enable 1 1: enable address learning capability of port 4 0: disable address learning capability of port 4 R/W Learning enable 1 1: enable address learning capability of port 3 0: disable address learning capability of port 3 R/W Learning enable 1 1: enable address learning capability of port 2 0: disable address learning capability of port 2 R/W Learning enable 1 1: enable address learning capability of port 1 0: disable address learning capability of port 1 R/W Learning enable 1 1: enable address learning capability of port 0 0: disable address learning capability of port 0 R/W Stag_en special tagging function enable 0 If this function is enabled, IP175C/IP175CH inserts source port information in tag header. 1: enable special tagging function 0: disable special tagging function R/W Forward enable 1 1: enable receiving function of port 4 0: disable receiving function of port 4 R/W Forward enable 1 1: enable receiving function of port 3 0: disable receiving function of port 3 R/W Forward enable 1 1: enable receiving function of port 2 0: disable receiving function of port 2 R/W Forward enable 1 1: enable receiving function of port 1 0: disable receiving function of port 1 R/W Forward enable 1 1: enable receiving function of port 0 0: disable receiving function of port 0
16.12
66.4
16.11
66.3
16.10
66.2
16.9
66.1
16.8
66.0
16.7
65.7
16.4
65.4
16.3
65.3
16.2
65.2
16.1
65.1
16.0
65.0
89/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY MII ROM 30 17[14:13] 11[5:4] R/W Description R/W Drive Pad driving capability selection 00: 4mA 01: 8mA 10: 12mA 11: 16mA
R/W DIGITAL_SPEED_UP Default value TEST2=0 0 17.10 10.4 R/W DIGITAL_LPBK TEST2=0 0 17.9 10.1 R/W BYSCR_MODE Default value TEST2=0 17.8 11.3 0 R/W F_LINK_100 TEST2=0 0 17.7 11.2 R/W F_LINK_10 Default value TEST2=0 0 17.6 11.1 R/W SPEED_UP_10 TEST2=0 0 17[5:0] 12[5:0] R/W TMOD_SEL Default value TEST2=0 6'b000000 TEST2=1
{pin64(0), pin65(0), pin67(0), pin100(0), pin101(0), pin102(0)}
Default 2'b0
17.12 17.11 10.5 *
TEST2=1 Pin79 DIGITAL_SPEED_UP(0) * Default value TEST2=1 Pin 84 DIGITAL_LPBK (0) * TEST2=1 Pin 109 BPSCR (0) * Default value TEST2=1 Pin 63 F_LINK_100N (0) * TEST2=1 Pin 59 F_LINK_10 (0) * Default value TEST2=1 Pin 80 SPEED_UP_10 (0) *
90/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 MII 18.15 18.14 18.13 18.12 18.11 18.10 18.9 18.8 18.7 ROM ----12.6 6.1 6.2 5.3 13.7 R/W RO RO RO RO R/W R/W R/W R/W R/W Description
mii1_full mii1_speed10 mii0_full mii0_speed10 allpass modbck twopart bp_kind Port5 VLAN look up table Port5 and port5 are in the same VLAN. This bit is "don't care". It is fixed "1". 18.6 13.6 R/W Port5 Class of service enable 1: enable, 0: disabled (default) Packets with high priority tag from Port5 are handled as high priority packets. Default value TEST2=0 P4EXT=1 0 18.5 13.5 TEST2=1 P4EXT=0 Pin 63 COS_EN (0) 0 1'b0 *
Default 1 0 0 1 0 1 1 0 1'b1
R/W Port5 set to be high priority port 1: enable, 0: disabled (default) Packets received from Port5 are handled as high priority packets. R/W Port5 VLAN look up table The register defines the ports in the same VLAN as port5. The bit 0~5 are corresponding to port 0~5. 1: a port is in the same VLAN as Port5 0: a port is not in the same VLAN as MI port Bit0=1, port 0 and Port5 are in the same VLAN; Bit1=1, port 1 and Port5 are in the same VLAN; Bit2=1, port 2 and Port5 are in the same VLAN; Bit3=1, port 3 and Port5 are in the same VLAN; Bit4=1, port 4 and Port5 are in the same VLAN; Bit5=1, don't care; Default value Test mode 38,39 6'b100011 Others 6'b111111
18[4:0]
13[4:0]
*
91/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30
30 30 30 30 30
MII 20
21 22 23 24 25
ROM 68 67 70 69 72 71 74 73 76 75 78 77
R/W R/W static_mac_0[15:0]
R/W static_mac_0[31:16] R/W static_mac_0[47:32] R/W static_mac_1[15:0] R/W static_mac_1[31:16] R/W static_mac_1[47:32]
Description
Default 16'h0000
16'hc200 16'h0180 16'h0000 16'h0000 16'h0000
92/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 R/W Description Default R/W static_overide_1 0 1: override the transmission, receiving and learning setting in MII register 30.16. 0: not override 26.14 80.6 R/W static_valid_1 0 1: the entry is valid 0: the entry is not valid 26[13:8] 80[5:0] R/W static_port_mask_1 6'b100000 Bit [13]: forward to port 5 (MII0) Bit [12]: forward to port 4 Bit [11]: forward to port 3 Bit [10]: forward to port 2 Bit [9]: forward to port 1 Bit [8]: forward to port 0 26.7 79.7 R/W static_overide_0 1 1: override the transmission, receiving and Learning setting in MII register 30.16. 0: not override 26.6 79.6 R/W static_valid_0 0 1: the entry is valid 0: the entry is not valid 26[5:0] 79[5:0] R/W static_port_mask_0 6'b100000 Bit [5]: forward to port 5 (MII0) Bit [4]: forward to port 4 Bit [3]: forward to port 3 Bit [2]: forward to port 2 Bit [1]: forward to port 1 Bit [0]: forward to port 0 MII 26.15 ROM 80.7
30
30
30
30
30
93/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 30 MII 27.8 ROM 5.0 R/W Description Default R/W MBSTM DISABLE 1 Multicast broadcast storm protection disable 1: "Broadcast storm protection" does not include multicast packets. IP175C/IP175CH drops the packets with DA = FFFFFFFF only when the broadcast threshold is reached (default), 0: "Broadcast storm protection" includes multicast packets. IP175C/IP175CH drops the packets with DA = FFFFFFFFF, or multi-cast address when the broadcast threshold is reached.
"Broadcast storm protection" does not drop packets due to not learned address. R/W DIFFSEV_EN 1: DiffServ is enabled, 0: Diffserv is disabled (default) R/W DSCP[15:0] Lookup table for DiffServ R/W DSCP[31:16] Lookup table for DiffServ R/W DSCP[47:32] Lookup table for DiffServ R/W DSCP[63:48] Lookup table for DiffServ
30 30 30 30 30
27.0 28 29 30 31
81.0 83, 82 85, 84 87, 86 89, 88
0 0 0 0 0
94/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY MII ROM R/W Description 31 2[14:12] 95[6:4] R/W BW_CONTROL_P5_TX[2:0] [2:0] BW, bps 64-byte 1518-byte ,bytes ,bytes
000 001 010 011 100 101 110 111 31 2[10:8] [2:0] Full rate 128 Kbps 256 Kbps 512 Kbps 1 Mbps 2 Mbps 4 Mbps 8 Mbps BW, bps
Default 000
random length ,bytes
Full rate Full rate Full rate 13,459 79,806 48,769 30,281 57,201 111,051 225,400 447,478 898,330 64-byte ,bytes Full rate 20,187 37,009 63,994 117,431 231,780 454,295 905,064 79,807 79,803 159,606 319,249 558,556 1,037,449 1518-byte ,bytes Full rate 159,622 159,621 159,610 239,414 399,013 638,412 1,117,149 52,955 87,182 148,281 273,923 508,248 1,009,446 000 random length ,bytes Full rate 92,156 100,183 131,723 192,672 314,536 561,996 1,062,681 000 000 000 000 000 000 000 000 000 000
95[2:0] R/W BW_CONTROL_P5_RX[2:0]
000 001 010 011 100 101 110 111 31 31 31 31 31 31 31 31 31 31 2[6:4] 2[2:0] 1[10:8] 1[6:4]
Full rate 128Kbps 256Kbps 512Kbps 1 Mbps 2 Mbps 4 Mbps 8 Mbps
94[6:4] R/W BW_CONTROL_P4_TX[2:0] 94[2:0] R/W BW_CONTROL_P4_RX[2:0] 93[2:0] R/W BW_CONTROL_P3_RX[2:0] 92[6:4] R/W BW_CONTROL_P2_TX[2:0]
1[14:12] 93[6:4] R/W BW_CONTROL_P3_TX[2:0]
1[2:0] 92[2:0] R/W BW_CONTROL_P2_RX[2:0] 0[14:12] 91[6:4] R/W BW_CONTROL_P1_TX[2:0] 0[10:8] 0[6:4] 0[2:0] 91[2:0] R/W BW_CONTROL_P1_RX[2:0] 90[6:4] R/W BW_CONTROL_P0_TX[2:0] 90[2:0] R/W BW_CONTROL_P0_RX[2:0]
95/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII0 MAC mode register PHY 31 MII 3.15 ROM -R/W Description Default RO Flow control capability of the link partner of external PHY on MII0 1 1: link partner supports flow control, 0: link partner does not support flow control RO Mac_force[0]
1: MII0's speed and duplex are forced because IP175C/IP175CH finds external PHY doesn't support SMI 0: MII0 polls external PHY through SMI to decide its speed and duplex.
31
3.14
--
31 31
3.13 3[12:8]
-98[4:0]
RO MII0_link 1: link ok, 0: un-link R/W Capability of external PHY on MII0 bit12: flow control ability, bit11: 100M full duplex, bit10 : 100M half duplex, bit9 : 10M full duplex, bit8: 10M half duplex RO Speed of external PHY on MII0 1: 10M, 0: 100M RO Duplex of external PHY on MII0 1: full duplex, 0: half duplex RO Link status of external PHY on MII0 1: link on, 0: link off R/W MII0_mac_phy_addr 11111
31
3.7
--
0
31
3.6
--
0
31
3.5
--
0
31
3[4:0]
97[4:0]
00000
96/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII1 MAC mode or MII2 MAC mode register (Only one is active at the same time.) PHY 31 R/W Description Default RO Flow control capability of the link partner of external PHY on MII1 1 MAC or MII2 MAC 1: link partner supports flow control, 0: link partner does not support flow control 4.14 -RO Mac_force[1] 1: MII1orMII2's speed and duplex are forced because IP175C/IP175CH finds external PHY doesn't support SMI 0: MII1orMII2 polls external PHY through SMI to decide its speed and duplex. 4.13 -RO MII1orMII2 _link 1: link ok, 0: un-link 4[12:8] 100[4:0] R/W Capability of external PHY on MII1 MAC or MII2 MAC 11111 bit12: flow control ability, bit11: 100M full duplex, bit10 : 100M half duplex, bit9 : 10M full duplex, bit8: 10M half duplex 4.7 -RO Speed of external PHY on MII1 MAC or MII2 MAC 0 1: 10M, 0: 100M 4.6 -RO Duplex of external PHY on MII1 MAC or MII2 MAC 0 1: full duplex, 0: half duplex 4.5 -RO Link status of external PHY on MII1 MAC or MII2 MAC 0 1: link on, 0: link off 4[4:0] 99[4:0] R/W MII1orMII2_mac_phy_addr 00001 MII 4.15 ROM --
31
31 31
31
31
31
31
97/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
MII1, MII1 and MII2 control register PHY 31 MII 5.15 ROM 7.0 R/W Description R/W P4EXT 1: enable 0: disable (default) SMI0_polling RO 1: MII0 MAC mode, 0: MII0 PHY mode RO SMI1_polling 1: MII1 MAC mode, 0: MII1 PHY mode R/W MII1_PHY_MOD 1: MII1 is connected to PHY4.0: MII1 is connected to MAC4. R/W MII0_mac_mode_en External MII0 port MAC mode 1: MII0 works as a MAC and should be connected to an external PHY. 0: MII0 works as a PHY and should be connected to an external MAC device (default). This bit does not affect MII1 port. Default value MII2_EN=1 MII2_EN=0 0 Pin96 MII0_MAC_MODE (0) R/W MII0_RMII_EN 1: MII0 RMII interface enabled 0: MII0 RMII interface disabled (default). Default value P4EXT=1 & RMII_EN=1 Others 1 0 R/W MII2_RMII_EN 1: MII2 RMII interface enabled 0: MII2 RMII interface disabled (default). Default value P4EXT=1 & RMII_EN=1 & MII2_EN=1 Others 1 0 R/W MII1_RMII_EN 1: MII1 RMII interface enabled 0: MII1 RMII interface disabled (default). Default value P4EXT=1 & RMII_EN=1 & MII1_DIS=0 Others 1 0 R/W MII1OR2_MAC_REPEATER 1: external PHY `s TXEN does not loop back to CRS (default) 0: external PHY `s TXEN loop back to CRS R/W MII0_MAC_REPEATER 1: external PHY `s TXEN does not loop back to CRS (default) 0: external PHY `s TXEN loop back to CRS Default Pin74
31 31 31 31
5.14 5.13 5.12 5.11
--7.4 60.2
Pin54(1) *
31
5.10
60.3
Pin(0)
31
5.9
3.5
*
31
5.8
3.4
*
31
5.7
3.3
1
31
5.6
3.2
1
98/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 31 MII 5.5 ROM 3.1 R/W Description R/W MII2_PHY_COL_DELAY 0: no delay, 1: collision delay 24 clocks (default) It is valid only if MII2 is enabled and it works at PHY mode. R/W MII0_PHY_COL_DELAY 0: no delay, 1: collision delay 24 clocks (default) It is valid only if MII0 is enabled and it works at PHY mode. R/W MII2_EN 1: enable, 0: disable (default) R/W SERIAL_LED_MODE 1: supports link, speed, and duplex LED 0: supports link LED only (default) R/W MII2_MAC_MOD 1: MII2 works in MAC mode 0: MII2 works in PHY mode (default) Default 1
31
5.4
3.0
1
31 31
5.2 5.1
2.4 2.3
Pin113(0) 0
31
5.0
2.2
Pin111(0)
99/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
PHY 31
31 31
MII 6[15]
6[14] 6.1
ROM --9.1
31
6.0
9.0
R/W Description Default RO MII1 flow control ability 1: enable, 0: disable RO MII0 flow control ability 1: enable, 0: disable R/W MDIX_FORCE 1 1: enable (default), 0: disable * R/W EN_AUTOMDIX 1: enable auto mdi/mdix function (default), It is valid only if MII 31.6.1 mdix_force is equal to 1 or Nway is enabled. 0: disable auto mdi/mdix function Default value TEST2=0 TEST2=1 1 Pin57 MDI_MDIX (0)
100/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3
3.1
Electrical Characteristics
Absolute Maximum Rating
Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to the device. Functional performance and device reliability are not guaranteed under these conditions. All voltages are specified with respect to GND. Supply Voltage Input Voltage Output Voltage Storage Temperature Ambient Operating Temperature (Ta) -0.3V to 4.0V -0.3V to 5.0V -0.3V to 5.0V -65C to 150C 0C to 70C
3.2
DC Characteristic
Sym. VCC VCC_O REG_OUT Min. 1.70 3.135 1.70 Typ. 1.80 3.3 1.80 1 Max. 2.00 3.465 2.00 Unit V V V W Conditions
Operating Conditions Parameter Supply Voltage Supply Voltage Regout Voltage Power Consumption Input Clock Parameter Frequency Frequency Tolerance Sym. Min.
-50
All ports link at 10Mbps mode VCC=1.8v
Typ. 25
Max.
+50
Unit MHz PPM
Conditions
I/O Electrical Characteristics Parameter Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage X1 Input Low Voltage X1 Input High Voltage Output Low Voltage Output High Voltage
FXSD4 Input Low Voltage FXSD4 Input High Voltage VIH 1 V
Sym. VIL VIH VIL VIH VIL VIH VOL VOH
VIL
Min.
2.1
Typ.
Max. 0.8
0.7
1.4 0.89 0.95 0.4 2.4 0.3
Unit V V V V V V V V V
Conditions
When VCC_IO = 3.3v When VCC_IO = 3.3v When VCC_IO = 1.95v When VCC_IO = 1.95v
IOH=4mA, VCC_O_x=3.3V IOL=4mA, VCC_O_x=3.3V
101/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3
3.3.1
AC Timing
Reset Timing Description Min.
10 10 -
Typ.
1
Max.
-
Unit
ms ms s
X1 valid period before reset released Reset period MII clock comes out period after reset released
Power on VCC OSCI (X1) X1 valid period before reset released
Reset released resetb Reset period
MII clock
MII clock comes out period after reset released
3.3.2
PHY Mode MII Timing
a. Transmit Timing Requirements
Symbol
TTxClk TTxClk TsTxClk ThTxClk
Description
Transmit clock period 100M MII Transmit clock period 10M MII TXEN, TXD to MII_TXCLK setup time TXEN, TXD to MII_TXCLK hold time
T T xC lk
Min.
2 0.5
Typ.
40 400 -
Max.
-
Unit
ns ns ns ns
M II_T X C LK T hT xC lk T X E N , T X D [3:0 ] T sT xC lk
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
b. Receive Timing
Symbol
TRxClk TRxClk TdRxClk
Description
Receive clock period 100M MII Receive clock period 10M MII MII_RXCLK falling edge to RXDV, RXD
TRxClk
Min.
1
Typ.
40 400 -
Max.
4
Unit
ns ns ns
MII_RXCLK TdRxClk RXDV, RXD[3:0]
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.3 MAC Mode MII Timing
a. Receive Timing Requirements
Symbol
TRxClk TRxClk TsRxClk ThRxClk
Description
Receive clock period 100M MII Receive clock period 10M MII RXDV, RXD to MII_RXCLK setup time RXDV, RXD to MII_RXCLK hold time
Min.
2 0.5
Typ.
40 400 -
Max.
-
Unit
ns ns ns ns
T R xC lk
M II_R X C LK T hR xC lk R X D V , R X D [3:0] T sR xC lk
b. Transmit Timing
Symbol
TTxClk TTxClk TdTxClk
Description
Transmit clock period 100M MII Transmit clock period 10M MII MII_TXCLK rising edge to TXEN, TXD
TTxClk MII_TXCLK TdTxClk
Min.
1
Typ.
40 400 -
Max.
4
Unit
ns ns ns
TXEN, TXD[3:0]
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.4 RMII Timing
a. Receive Timing Requirements
Symbol
TRxClk TsRxClk ThRxClk
Description
Receive clock period RXDV, RXD to MII_CLK_IN setup time RXDV, RXD to MII_CLK_IN hold time
T R xC lk
Min.
2 0.5
Typ.
20 -
Max.
-
Unit
ns ns ns
M II_C LK _IN T hR xC lk R X D V , R X D [1:0] T s R xC lk
b. Transmit Timing
Symbol
TTxClk TdTxClk
Description
Transmit clock period MII_CLK_IN rising edge to TXEN, TXD
Min.
1
Typ.
20 -
Max.
4
Unit
ns ns
TTxClk
MII_CLK_IN TdTxClk TXEN, TXD[1:0]
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.5 SNI Timing
a. Transmit Timing Requirements
Symbol
TTxClk TsTxClk ThTxClk
Description
Transmit clock period TXEN, TXD to MII_TXCLK setup time TXEN, TXD to MII_TXCLK hold time
T T xC lk
Min.
2 0.5
Typ.
100 -
Max.
-
Unit
ns ns ns
M II_T X C LK T hT xC lk T X E N , T X D [0] T sT xC lk
b. Receive Timing
Symbol
TRxClk TdRxClk
Description
Receive clock period MII_RXCLK rising edge to RXDV, RXD
TRxClk
Min.
1
Typ.
100 -
Max.
4
Unit
ns ns
MII_RXCLK TdRxClk RXDV, RXD[0]
106/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.6 SMI Timing
a. MDC0/MDIO0 Timing
Symbol
Tch Tcl Tcm Tmd Tmh Tms
Description
MDC0 High Time MDC0 Low Time MDC0 period MDIO0 output delay MDIO0 setup time MDIO0 hold time
Min.
40 40 80 10 10
Typ.
-
Max.
5 -
Unit
ns ns ns ns ns ns
MDC0 T ms T mh
M D IO 0
W r ite C yc le
MDC0 T cl T cm T ch T md
M D IO 0
R e a d C yc le
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
b. MDC1/ MDIO1 Timing
Symbol
Tch Tcl Tcm Tmd Tms Tmh
Description
MDC1 High Time MDC1 Low Time MDC1 period MDIO1 output delay MDIO1 setup time MDIO1 hold time
Min.
40 40 80 10 10
Typ.
-
Max.
5 -
Unit
ns ns ns ns ns ns
MDC1 Tms M D IO 1 T mh
W r ite C yc le
MDC1 T cl T cm M D IO 1 T ch T md
R e a d C yc le
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Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
3.3.7 EEPROM Timing
a.
Symbol
TSCL TsSCL ThSCL
Description
Receive clock period SDA to SCL setup time SDA to SCL hold time
T SCL
Min.
2 0.5
Typ.
20480 -
Max.
-
Unit
ns ns ns
SCL T hS C L SDA T sSC L
R ead data cycle
b.
Symbol
TSCL TdSCL
Description
Transmit clock period SCL falling edge to SDA
Min.
-
Typ.
20480 -
Max.
5200
Unit
ns ns
TSCL SCL TdSCL SDA
Comand cycle
3.4
Thermal Data
Theta Ja 38.2 Theta Jc -Conditions 2 Layer PCB Units o C/W
109/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
4 Order Information
Part No. IP175C IP175C LF IP175CH IP175CH LF Package 128-PIN PQFP 128-PIN PQFP 128-PIN PQFP 128-PIN PQFP Notice Lead free
For fiber applicationFor fiber application
Lead free
110/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14
IP175C/IP175C LF/IP175CH/IP175CH LF
Data Sheet
5 Package Detail
HD D
128 103
128 PQFP Outline Dimensions
1
102
38
65
39
64
e
b GAGE PLANE A2 A1
c
HE
E
Symbol A1 A2 b c HD D HE E e L L1 y
Dimensions In Inches Min. Nom. Max. 0.010 0.014 0.018 0.107 0.112 0.117 0.007 0.009 0.011 0.004 0.006 0.008 0.669 0.677 0.685 0.547 0.551 0.555 0.906 0.913 0.921 0.783 0.787 0.791 0.020 0.025 0.035 0.041 0.063 0.004 0 12
Dimensions In mm Min. Nom. Max. 0.25 0.35 0.45 2.73 2.85 2.97 0.17 0.22 0.27 0.09 0.15 0.20 17.00 17.20 17.40 13.90 14.00 14.10 23.00 23.20 23.40 19.90 20.00 20.10 0.50 0.65 0.88 1.03 1.60 0.10 0 12
D
L1
L
y
Note: 1. Dimension D & E do not include mold protrusion. 2. Dimension B does not include dambar protrusion. Total in excess of the B dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
IC Plus Corp.
Headquarters 10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2, Hsin-Chu City, Taiwan 300, R.O.C. TEL : 886-3-575-0275 FAX : 886-3-575-0475 Website: www.icplus.com.tw Sales Office 4F, No. 106, Hsin-Tai-Wu Road, Sec.1, Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C. TEL : 886-2-2696-1669 FAX : 886-2-2696-2220
111/111 Copyright (c) 2004, IC Plus Corp.
Mar 09, 2007 IP175C/IP175CH-DS-R14

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